ADP1048WARQZ-R7 datasheet(32/82 Pages) AD

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ADP1048W

Data Sheet

BRIDGELESS BOOST OPERATION

The bridgeless boost configuration allows removal of the con-

duction losses caused by the input bridge of the PFC converter.

In this configuration, it is necessary to drive the two power

MOSFETs separately to achieve the highest efficiency. The

ADP1048W can provide such signals. The IBAL pin is used to

detect the ac line phase and zero crossings. Note that the maxi-

mum rating on the IBAL pin is VDD + 0.3 V; therefore, a clamp

circuit must be connected to the IBAL pin.

During the positive ac line phase, only one boost stage is effec-

tively working. The second one is passive, and the current flows in

Q2 from the source to the drain. Turning the Q2 FET fully on

during this phase allows conduction losses in Q2 to be minimized.

When the ac line phase becomes negative, the roles of Q1 and Q2

are reversed, and Q2 actively switches while Q1 is always on. The

phase information is detected from the ac line via the IBAL pin.

During the soft start phase, both FETs are switching as a precau-

tionary measure; the same happens when the phase information

on the IBAL pin becomes corrupted or inaccurate.

Figure 30. Schematic of Bridgeless PFC Circuit

Figure 31. Bridgeless Boost Operation

RES

RTD

ADD

SYNC

INRUSH

SCL

SDA

VAC

VFB

OVP

IBAL

ILIM

PGND

AGND

CS–

PSON

DGND

CS+

PWM2

VCORE

PWM

AC_OK

PGOOD

VDD

ADP1048W

VREC

RELAY

VOUT

BULK

CAPACITOR

T1 + T2 + T3

3.3V

PMBus

INPUT

VAC

IBAL PIN

PWM

PWM2

Rev. 0 | Page 32 of 82

ADP1048WARQZ-R7 数据表(PDF) 32 Page - Analog Devices

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