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ADP1048WARQZ-R7 数据表(PDF) 79 Page - Analog Devices |
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ADP1048WARQZ-R7 数据表(HTML) 79 Page - Analog Devices |
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79 / 82 page  Data Sheet ADP1048W Table 149. Register 0xFE82—Latched Flag 2 Bits Bit Name R/W Description [7:6] RSVD R Reserved. 5 LOW_POWER R 1 = input power has dropped below the threshold for low power mode operation. 4 FAST_LOOP R 1 = fast loop compensation filter is in use. 3 VCORE_OV R 1 = an overvoltage condition is present on the VCORE rail. 2 VDD_3.3V_OV R 1 = an overvoltage condition is present on the VDD rail. 1 VDD_3.3V_UV R 1 = an undervoltage condition is present on the VDD rail. 0 RSVD R Reserved. PWM VALUE REGISTER Table 150. Register 0xFE84—PWM Value Bits Bit Name R/W Description [7:0] PWM value R Return the eight MSBs of the PWM value (10 bits). VAC_LINE_PERIOD REGISTER Table 151. Register 0xFE85—VAC_LINE_PERIOD Bits Bit Name R/W Description [7:0] VAC line period R Return the measured period on the VAC pin signal. Each LSB corresponds to 163.84 μs. READ TEMPERATURE ADC REGISTER Table 152. Register 0xFE86—Read Temperature ADC Bits Bit Name R/W Description [15:0] RTD temperature R Return the measured temperature in ADC 13-bit format. POWER METERING OFFSET TRIM FOR HIGH LINE INPUT REGISTER Table 153. Register 0xFE8E—Power Metering Offset Trim for High Line Input Bits Bit Name R/W Description 7 Offset trim polarity R/W 1 = negative offset trim is introduced. 0 = positive offset trim is introduced. [6:0] Power meter offset trim R/W This value calibrates the power meter offset at the high line input voltage. Each LSB corresponds to 0.0625/128 of the full input power. POWER METERING GAIN TRIM FOR HIGH LINE INPUT REGISTER Table 154. Register 0xFE8F—Power Metering Gain Trim for High Line Input Bits Bit Name R/W Description 7 Gain trim polarity R/W 1 = negative gain trim is introduced. 0 = positive gain trim is introduced. [6:0] Power meter gain trim R/W This value calibrates the power meter gain at the high line input voltage. Each LSB corresponds to 0.0625/128 of the input power. CURRENT LOOP FILTER GAIN FOR LOW LINE INPUT AND LIGHT LOAD REGISTER Table 155. Register 0xFE90—Current Loop Filter Gain for Low Line Input and Light Load Bits Bit Name R/W Description [7:0] Current loop filter gain for low line and light load R/W These bits set the current loop digital filter gain of the PFC current loop under the low line input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1. Rev. 0 | Page 79 of 82 |
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