ADP1048WARQZ-R7 datasheet(12/82 Pages) AD

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ADP1048W

Data Sheet

CONTROLLER ARCHITECTURE

The ADP1048W integrates the following functions:

•

Power factor correction control loop (see the Power Factor

Correction Control Loop section)

•

Advanced input power metering (see the Advanced Input

Power Metering section)

•

PMBus digital communication (see the PMBus Digital

Communication section)

This section describes the internal architecture of the chip.

CURRENT SENSE

Current sensing is used for the control, protection, and monitor-

ing of the PFC stage. For normal operation, the power factor

correction control loop requires inductor current information.

The typical implementation uses a sense resistor on the input

bus. A combination of two current transformers in series with

the power switch and the boost diode can be used to reconstruct

the inductor current and minimize losses in the resistive shunt,

but, in general, a good quality shunt resistor provides much

better accuracy in measuring input current and input power.

The inputs to the current sense ADC are differential. A pair of

matched current sources is provided to level shift the negative

signal across the current sense element in the input range of the

current sense ADC (see Figure 4).

Figure 4. Current Sense Configuration

The current sense can be calibrated digitally to remove any

errors due to external components (see the Current Sense Gain

and Offset Trim section). This calibration can be performed in

the production environment; the settings are saved in the

EEPROM of the ADP1048W.

The output of the Σ-Δ ADC is used for the following purposes:

•

The output is decimated at the switching frequency for the

control loop. The effective number of bits (ENOB) is >7

when the current loop bandwidth is 10 kHz; the ENOB

is >10 when the current loop bandwidth is 1 kHz.

•

The 11-bit result is calculated and updated at each half line

cycle for high accuracy ac line current and input power

monitoring and for overcurrent protection (accurate OCP).

RMS INPUT OVERCURRENT PROTECTION

The ADP1048W provides rms overcurrent protection (OCP).

RMS OCP (or accurate OCP) is distinct from the instantaneous

pulse-by-pulse fast overcurrent protection and is based on the

rms value of the input ac current.

The measured value is compared to the limit set in the

IIN_OC_FAULT_LIMIT register (Register 0x5B) at the

end of each half cycle of the ac line. If the limit is exceeded,

the action programmed in the IIN_OC_FAULT_RESPONSE

In addition, an input current warning limit can be programmed

in the IIN_OC_WARN_LIMIT register (Register 0x5D). This

warning limit has no action attached to it, but it sets flags in the

STATUS_BYTE register (Register 0x78, Bit 0), the STATUS_WORD

(Register 0x7C, Bit 1).

FAST OVERCURRENT PROTECTION (ILIM PIN)

A dedicated current limiting pin (ILIM) is provided to protect

the decice from pulse-by-pulse overcurrent events. When the

threshold is crossed, the PWM pulse is terminated. This action

is independent of any programming of the fast OCP flag. The

next switching cycle resumes normally. Additional actions can

be programmed (see Table 5).

The OCP comparator on the ILIM pin can accept positive or

negative signals; the pin is referred to PGND (power ground) and

has programmable level shifting current sources (see Table 5).

These sources can be changed during normal operation to adapt

to the level at which the overcurrent protection is triggered.

The OCP comparator also features programmable blanking and

debounce times (see Table 5). If OCP is triggered, the PWM

signal is terminated and operation resumes at the next switch-

ing cycle unless a different action is specified for the fast OCP

response in Register 0xFE00.

11-BIT

ADC

CS–

CS+

10kΩ

VDD

–

ADP1048W

Rev. 0 | Page 12 of 82

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