ADP1048WARQZ-R7 datasheet(77/82 Pages) AD

77 / 82 page

Data Sheet

ADP1048W

POWER_HYS REGISTER

Table 139. Register 0xFE4E—POWER_HYS

Bits

Bit Name

R/W

Description

[7:0]

Power hysteresis

R/W

These bits set the power hysteresis for low power mode operation. The PFC exits the low power

mode if the input power is higher than the low power threshold plus the power hysteresis.

ADVANCED FEATURE ENABLE REGISTER

Table 140. Register 0xFE4F—Advanced Feature Enable

Bits

Bit Name

R/W

Description

RSVD

Reserved.

Enable current loop

feedforward

R/W

1 = current loop feedforward is enabled.

0 = current loop feedforward is disabled.

Enable light load

current loop filter

R/W

1 = light load current loop filter is enabled.

0 = light load current loop filter is disabled.

Enable phase shedding

R/W

1 = phase shedding is enabled.

0 = phase shedding is disabled.

Enable smart switching

frequency

R/W

1 = smart switching frequency is enabled.

0 = smart switching frequency is disabled.

Enable smart output

voltage

R/W

1 = smart output voltage is enabled.

0 = smart output voltage is disabled.

Enable PWM

synchronization

R/W

1 = PWM frequency synchronization is enabled.

0 = PWM frequency synchronization is disabled.

Enable frequency

dithering

R/W

1 = frequency dithering is enabled.

0 = frequency dithering is disabled.

VOUT_OV_FAULT_HYS REGISTER

Table 141. Register 0xFE50—VOUT_OV_FAULT_HYS

Bits

Bit Name

R/W

Description

[7:0]

VOUT OV fault hysteresis

R/W

This register determines the mantissa hysteresis for the VOUT_OV_FAULT_LIMIT condition. This

hysteresis applies only when the disable output option is selected as the VOUT_OV_FAULT_

RESPONSE (Register 0x41, Bits[7:6]). The PFC output is reenabled when the output voltage is

lower than VOUT_OV_FAULT_LIMIT minus this hysteresis.

VIN_UV_FAULT_HYS REGISTER

Table 142. Register 0xFE51—VIN_UV_FAULT_HYS

Bits

Bit Name

R/W

Description

[7:0]

VIN UV fault hysteresis

R/W

This register determines the mantissa hysteresis for the VIN_UV_FAULT_LIMIT condition. This

hysteresis applies only when the disable output option is selected as the VIN_UV_FAULT_

RESPONSE (Register 0x5A, Bits[7:6]). The PFC output is reenabled when the input voltage is

higher than VIN_UV_FAULT_LIMIT plus this hysteresis.

VAC ADC OFFSET TRIM REGISTER

This register must be unlocked for write access; see Table 61.

Table 143. Register 0xFE53—VAC ADC Offset Trim

Bits

Bit Name

R/W

Description

[7:0]

VAC ADC offset trim

R/W

This register calibrates the VAC ADC offset (the offset is always subtracted from the ADC output).

Rev. 0 | Page 77 of 82

ADP1048WARQZ-R7 数据表(PDF) 77 Page - Analog Devices

ADP1048WARQZ-R7 数据表(HTML) 77 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

数据表下载

链接网址

ADP1048WARQZ-R7 数据表(PDF) 77 Page - Analog Devices

ADP1048WARQZ-R7 数据表(HTML) 77 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

数据表 下载

链接网址

数据表下载