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ADP1048WARQZ-R7 数据表(PDF) 80 Page - Analog Devices |
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ADP1048WARQZ-R7 数据表(HTML) 80 Page - Analog Devices |
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80 / 82 page  ADP1048W Data Sheet CURRENT LOOP FILTER ZERO FOR LOW LINE INPUT AND LIGHT LOAD REGISTER Table 156. Register 0xFE91—Current Loop Filter Zero for Low Line Input and Light Load Bits Bit Name R/W Description [7:0] Current loop filter zero for low line and light load R/W These bits set the current loop digital filter zero of the PFC current loop under the low line input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1. CURRENT LOOP FILTER GAIN FOR HIGH LINE INPUT AND LIGHT LOAD REGISTER Table 157. Register 0xFE92—Current Loop Filter Gain for High Line Input and Light Load Bits Bit Name R/W Description [7:0] Current loop filter gain for high line and light load R/W These bits set the current loop digital filter gain of the PFC current loop under the high line input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1. CURRENT LOOP FILTER ZERO FOR HIGH LINE INPUT AND LIGHT LOAD REGISTER Table 158. Register 0xFE93—Current Loop Filter Zero for High Line Input and Light Load Bits Bit Name R/W Description [7:0] Current loop filter zero for high line and light load R/W These bits set the current loop digital filter zero of the PFC current loop under the high line input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1. SMART VOUT POWER READING REGISTER Table 159. Register 0xFE94—Smart VOUT Power Reading Bits Bit Name R/W Description [15:0] Power reading R Return the average power reading for smart output voltage (averaged over 16 full line cycles). IBAL CONFIGURATION REGISTER Table 160. Register 0xFE95—IBAL Configuration Bits Bit Name R/W Description 7 IBAL disconnect R/W 1 = disconnect the output of the current balance block from the PWM outputs. 0 = connect the output of the current balance block to the PWM outputs. 6 IBAL at load transient R/W 0 = disable current balancing when the fast loop is triggered. 1 = enable current balancing when the fast loop is triggered. It is recommended that this bit be set to 0. [5:4] RSVD R Reserved. 3 IBAL at low power mode R/W 1 = disable current balancing under low power mode if the output of the current balancing block reaches the limit. 0 = enable current balancing under low power mode even if the output of the current balancing block reaches the limit. It is recommended that this bit be set to 1. [2:0] RSVD R Reserved. DEBUG FLAG REGISTERS Table 161. Register 0xFE96—Debug Flag 0 Bits Bit Name R/W Description 7 OT_WARN R 1 = measured temperature is above the value of OT_WARN_LIMIT. 6 OT_FAULT R 1 = measured temperature is above the value of OT_FAULT_LIMIT. 5 TEMPERATURE R 1 = temperature fault or warning. 4 UNKNOWN R 1 = fault or warning not listed in Register 0x79, Bits[15:1]. 3 MFR_FAULT R 1 = manufacturer-specific fault or warning (Register 0xFE80, Register 0xFE81, Register 0xFE82). 2 PSON R 1 = PSON signal (hardware or software) is inactive. 1 PGOOD R Power good. This flag is a programmable combination of other internal flags and refers to the condition of the output voltage. A value of 1 means that the output of the PGOOD pin is low. 0 AC_OK R This flag is a programmable combination of other internal flags and refers to the condition of the input voltage. A value of 1 means that the output of the AC_OK pin is low. Rev. 0 | Page 80 of 82 |
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