ADP5043ACPZ-1-R7 datasheet(24/30 Pages) AD

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ADP5043

Data Sheet

Rev. C | Page 24 of 30

Watchdog Software Considerations

In implementing the watchdog strobe code of the

microprocessor, quickly switching WDI1 low-to-high and

then high-to-low (minimizing WDI1 high time) is desirable

for current consumption reasons. However, a more effective

way of using the watchdog function can be considered.

A low-to-high-to-low WDI1 pulse within a given subroutine

prevents the watchdog from timing out. However, if the sub-

routine becomes stuck in an infinite loop, the watchdog cannot

detect this because the subroutine continues to toggle WDI1. A

more effective coding scheme for detecting this error involves

using a slightly longer watchdog timeout. In the program that

calls the subroutine, WDI1 is set high. The subroutine sets

WDI1 low when it is called. If the program executes without error,

WDI1 is toggled high and low with every loop of the program.

If the subroutine enters an infinite loop, WDI1 is kept low, the

watchdog times out, and the microprocessor is reset (see

Figure 53).

START

SET WDI

HIGH

PROGRAM

CODE

SUBROUTINE

SET WDI

LOW

RETURN

INFINITE LOOP:

WATCHDOG

TIMES OUT

RESET

Figure 53. Watchdog Flow Diagram

The second watchdog, refreshed through the WDI2 pin, is

useful in applications where safety is a very critical factor and

the system must recover from unexpected operations, for example,

a processor stuck in a continuous loop where Watchdog 1 is

kept refreshed or environmental conditions that may unset or

damage the processor port controlling the WDI1 pin. In the

event of a Watchdog 2 timeout, the ADP5043 power cycles all

the supplied rails to guarantee a clean processor start.

PCB LAYOUT GUIDELINES

Poor layout can affect the ADP5043 performance, causing

electro-magnetic interference (EMI) and electromagnetic

compatibility (EMC) problems, ground bounce, and voltage

losses. Poor layout can also affect regulation and stability. A

good layout is implemented using the following guidelines:



Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies, and large tracks act as antennas.



Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.



Maximize the size of ground metal on the component side

to help with thermal dissipation.



Use a ground plane with several vias connecting to the

component side ground to further reduce noise interference

on sensitive circuit nodes.

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