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ADP5043ACPZ-1-R7 数据表(PDF) 27 Page - Analog Devices |
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ADP5043ACPZ-1-R7 数据表(HTML) 27 Page - Analog Devices |
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27 / 30 page ![]() Data Sheet ADP5043 Rev. C | Page 27 of 30 EVALUATION BOARD SCHEMATICS AND ARTWORK SW VOUT1 PGND MODE C6 10µF L1 1µH VIN1 TP1 TP2 TP6 TP5 NC EN1 VIN2 EN2 C2 1µF VOUT2 TP12 NC C5 4.7µF VIN1 = 2.3V TO 5.5V AVIN RFILT 30Ω VIN2 = 1.7V TO 5.5V C1 1µF TP4 TP11 WSTAT WMOD WDI1 WDI2 nRSTO TP9 TP10 TP7 TP3 TP8 EN_BK BUCK EN_LDO LDO AVIN AVIN GND GND AGND MR VOUT1 @ 800mA VOUT2 @ 300mA Figure 54. Evaluation Board Schematic SUGGESTED LAYOUT 0.5 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 1 1.5 2 2.5 3 3.5 mm C3 - 1uF 6.3V/XR 5 0402 C4 - 1uF 10V/XR 5 0402 mm 5.5 6 6.5 AVIN VIN 1 SW PGND MR WDI 1 WMOD MODE AGND EN 1 GND 4 4.5 5 5.5 6 C6 - 10uF 6.3V/XR5 0603 3.3V WDI 1 MOD 1.5V MR - 1u V/XR 402 7 TOP LAYER 2ND LAYER EN ADP5043 MODE G VIAs LEGEND: PPL = POWER PLANE (+4V) GPL = GROUND PLANE Figure 55. Layout |
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