ADP5043ACPZ-1-R7 datasheet(26/30 Pages) AD

26 / 30 page

ADP5043

Data Sheet

Rev. C | Page 26 of 30

Switching losses are associated with the current drawn by the

driver to turn on and turn off the power devices at the switching

frequency. The amount of switching power loss is given by:

PSW = (CGATE-P + CGATE-N) × VIN12 × fSW

(10)

where:

CGATE-P is the PMOSFET gate capacitance.

CGATE-N is the NMOSFET gate capacitance.

For the ADP5043, the total of (CGATE-P + CGATE-N) is ~150 pF.

The transition losses occur because the PMOSFET cannot be

turned on or off instantaneously, and the SW node takes some

time to slew from near ground to near VOUT1 (and from VOUT1 to

ground). The amount of transition loss is calculated by:

PTRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW

(11)

where tRISE and tFALL are the rise time and the fall time of the

switching node, SW. For the ADP5043, the rise and fall times of

SW are in the order of 5 ns.

If the equations and parameters previously given are used for

estimating the converter efficiency, it must be noted that the

equations do not describe all of the converter losses, and the

parameter values given are typical numbers. The converter

performance also depends on the choice of passive components

and board layout, so a sufficient safety margin should be

included in the estimate.

LDO Regulator Power Dissipation

The power loss of a LDO regulator is given by:

PDLDO = [(VIN − VOUT) × ILOAD] + (VIN × IGND)

(12)

where:

ILOAD is the load current of the LDO regulator.

VIN and VOUT are input and output voltages of the LDO,

respectively.

IGND is the ground current of the LDO regulator.

Power dissipation due to the ground current is small and it

can be ignored.

Junction Temperature

The total power dissipation in the ADP5043 simplifies to:

PD = {[PDBUCK + PDLDO1 + PDLDO2]}

(13)

In cases where the board temperature (TA) is known, the

thermal resistance parameter, θJA, can be used to estimate the

junction temperature rise. TJ is calculated from TA and PD using

the formula:

TJ = TA + (PD × θJA)

(14)

The typical θJA value for the 20-lead, 4 mm × 4 mm LFCSP is

38°C/W, see Table 7.

An important factor to consider is that θJA is based on a four-

layer 4 inch × 3 inch, 2.5 oz copper, as per JEDEC standard, and

real applications may use different sizes and layers. It is

important to maximize the copper used to remove the heat from

the device, and copper exposed to air dissipates heat better than

copper used in the inner layers. The thermal pad (TP) should

be connected to the ground plane with several vias as shown in

Figure 55.

If the case temperature can be measured, the junction

temperature is calculated by:

TJ = TC + (PD × θJC)

(15)

where:

TC is the case temperature.

θJC is the junction-to-case thermal resistance provided in

Table 7.

When designing an application for a particular ambient

temperature range, calculate the expected ADP5043 power

dissipation (PD) due to the losses of all channels by using

Equation 8 to Equation 13. From this power calculation, the

junction temperature, TJ, can be estimated using Equation 14.

The reliable operation of the buck regulator and the LDO

regulator can be achieved only if the estimated die junction

temperature of the ADP5043 (Equation 14) is less than 125°C.

Reliability and mean time between failures (MTBF) is highly

affected by increasing the junction temperature. Additional

information about product reliability can be found in the

Analog Devices, Inc., Reliability Handbook.

ADP5043ACPZ-1-R7 数据表(PDF) 26 Page - Analog Devices

ADP5043ACPZ-1-R7 数据表(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

数据表下载

链接网址

ADP5043ACPZ-1-R7 数据表(PDF) 26 Page - Analog Devices

ADP5043ACPZ-1-R7 数据表(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

数据表 下载

链接网址

数据表下载