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ADP5043ACPZ-1-R7 数据表(PDF) 22 Page - Analog Devices

部件名 ADP5043ACPZ-1-R7
功能描述  Micro PMU with 800 mA Buck, 300 mA LDO, Supervisory, Watchdog, and Manual Reset
PDF  30 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP5043ACPZ-1-R7 数据表(HTML) 22 Page - Analog Devices

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ADP5043
Data Sheet
Rev. C | Page 22 of 30
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:


1/ 8
RIPPLE
RIPPLE
COUT
SW
OUT
VI
ESR
f
C

where:
VRIPPLE
is allowable peak-to-peak output voltage ripple in volts.
IRIPPLE
is the inductor ripple current in Amperes.
ESRCOUT
is the equivalent series resistance of the output
capacitor in Ω.
fSW
is the converter switching frequency in Hertz.
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 7 μF and a
maximum of 40 μF.
Table 12. Suggested 10 μF Capacitors
Vendor
Type
Model
Case
Size
Voltage
Rating (V)
Murata
X5R
GRM188R60J106
0603
6.3
Taiyo Yuden
X5R
JMK107BJ475
0603
6.3
TDK
X5R
C1608JB0J106K
0603
6.3
Panasonic
X5R
ECJ1VB0J106M
0603
6.3
The buck regulator requires 10 μF output capacitors to guaran-
tee stability and response to rapid load variations and to transition
in and out the PWM/PSM modes. In certain applications, where
the buck regulator powers a processor, the operating state is
known because it is controlled by software. In this condition,
the processor can drive the MODE pin according to the operating
state; consequently, it is possible to reduce the output capacitor
from 10 μF to 4.7 μF because the regulator does not expect a
large load variation when working in PSM mode (see Figure 50).
SW
VIN1
VIN2
VOUT1
VOUT2
nRSTO
PGND
L1
1µH
C6
4.7µF
C4
1µF
R1
100kΩ
C2
4.7µF
C3
1µF
AVIN
RFILT
30Ω
MICRO PMU
ADP5043
PROCESSOR
VCORE
VDDIO
RESET
GPIO1
MODE
WDIx
GPIO2
ENx
GPIO[x:y]
2
VIN
2.3V TO 5.5V
Figure 50. Processor System Power Management with PSM/PWM Control
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response. Maximum input
capacitor current is calculated using the following equation:
IN
OUT
IN
OUT
MAX
LOAD
CIN
V
V
V
V
I
I
)
(
)
(
To minimize supply noise, place the input capacitor as close
to the VIN pin of the buck as possible. As with the output
capacitor, a low ESR input capacitor is recommended.
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 3 μF and a
maximum of 10 μF. Suggested capacitors are shown in Table 13.
Table 13. Suggested 4.7 μF Capacitors
Vendor
Type
Model
Case
Size
Voltage
Rating
(V)
Murata
X5R
GRM188R60J475ME19D
0603
6.3
Taiyo Yuden
X5R
JMK107BJ475
0603
6.3
Panasonic
X5R
ECJ-0EB0J475M
0402
6.3
LDO CAPACITOR SELECTION
Output Capacitor
The ADP5043 LDO is designed for operation with small, space-
saving ceramic capacitors but functions with most commonly
used capacitors as long as care is taken with the
ESR value. The ESR of the output capacitor affects stability of
the LDO control loop. A minimum of 0.70 μF capacitance
with an ESR of 1 Ω or less is recommended to ensure stability
of the LDO. Transient response to changes in load current is
also affected by output capacitance. Using a larger value of
output capacitance improves the transient response of the
LDO to large changes in load current.
Input Bypass Capacitor
Connecting a 1 μF capacitor from VIN2 to GND reduces
the circuit sensitivity to printed circuit board (PCB) layout,
especially when long input traces or high source impedance
is encountered. If greater than 1 μF of output capacitance is
required, increase the input capacitor to match it.
Table 14. Suggested 1.0 μF Capacitors
Vendor
Type
Model
Case
Size
Voltage
Rating
(V)
Murata
X5R
GRM155R61A105ME15
0402
10.0
TDK
X5R
C1005JB0J105KT
0402
6.3
Panasonic
X5R
ECJ0EB0J105K
0402
6.3
Taiyo Yuden
X5R
LMK105BJ105MV-F
0402
10.0



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