ADP5043ACPZ-1-R7 datasheet(16/30 Pages) AD

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ADP5043

Data Sheet

Rev. C | Page 16 of 30

THEORY OF OPERATION

SOFT START

PWM/PSM

CONTROL

BUCK1

DRIVER

AND

ANTISHOOT

THROUGH

OSCILLATOR

VREF

THERMAL

SHUTDOWN

SYSTEM

UNDERVOLTAGE

LOCK OUT

RESET

GENERATOR

DEBOUNCE

PWM

COMP

VDDA

GM ERROR

AMP

PSM

COMP

LOW

CURRENT

ILIMIT

ADP5043

VOUT1

WMOD

ENWD1

ENWD2

VIN1

AVIN

PGND

EN1

ENBK

ENLDO

MODE

EN2

SEL

OPMODE_FUSES

AGND

VIN2

LDO

CONTROL

ENBK

75Ω

ENLDO

600Ω

VDDA

WDI1

200kΩ

VDDA

52kΩ

40kΩ

WATCHDOG

STATUS

MONITOR

WDI2

POFF

VOUT2

nRSTO

WSTAT

ENABLE

AND MODE

CONTROL

WATCHDOG

DETECTOR1

WATCHDOG

DETECTOR2

Figure 43. Functional Block Diagram

POWER MANAGEMENT UNIT

The ADP5043 is a micro power management unit (micro PMU)

combing one step-down (buck) dc-to-dc regulator, one low

dropout linear regulator (LDO), and a supervisory circuit with dual

watchdog, for processor control. The regulators are activated by a

logic level high applied to the respective EN pins. EN1 controls

the buck regulator while EN2 controls the LDO. The ADP5043

has factory programmed output voltages and reset voltage

threshold. Other features available in this device are the MODE

pin to control the buck switching operation, a status pin (WSTAT)

informing the external processor of which watchdog caused a

reset, and a push-button reset input (nRSTO).

When a regulator is turned on, the output voltage is controlled

through a soft start circuit, which prevents a large inrush current

due to the discharged output capacitors.

The buck regulator can operate in forced PWM mode if the

MODE pin is at a logic high level. In forced PWM mode, the

switching frequency of the buck is always constant and does not

change with the load current. If the MODE pin is at a logic low

level, the switching regulator operates in auto PWM/PSM mode.

In this mode, the regulator operates at fixed PWM frequency

when the load current is above the power saving current threshold.

When the load current falls below the power saving current

threshold, the regulator enters power saving mode where the

switching occurs in bursts. The burst repetition rate is a

function of the current load and the output capacitor value.

This operating mode reduces the switching and quiescent

current losses.

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