ADP5043ACPZ-1-R7 datasheet(20/30 Pages) AD

20 / 30 page

ADP5043

Data Sheet

Rev. C | Page 20 of 30

Watchdog Status Indicator

In addition to the dual watchdog function, the ADP5043 features a

watchdog status monitor available on the WSTAT pin. This pin

can be queried by the external processor to determine the origin of

a reset. WSTAT is an open-drain output.

WSTAT outputs a logic level depending on the condition

that has generated a reset. WSTAT is forced low if the reset

was generated because of a Watchdog 2 timeout. WSTAT is

pulled high, through external pull-up, for any other reset cause

(Watchdog 1 timeout, power failure or monitored voltage be

low threshold). The status monitor is automatically cleared

(set to logic level high) 10 seconds after the nRSTO low-to-high

transition (tWDCLEAR). The processor firmware must be designed

to read the WSTAT flag before tWDCLEAR expiration after a

Watchdog 2 reset.

The WSTAT flag is not updated in the event of a reset due to a

low voltage threshold detection or Watchdog 1 event occurring

within 10 seconds after an nRSTO low-to-high transition. In

this situation, WSTAT maintains the previous state (see the state

flow in Figure 47).

The external processor can further distinguish a reset caused

by a Watchdog 1 timeout from a power failure, status monitor

WSTAT indicating a high level, by implementing a RAM check

or signature verification after reset. A RAM check or signature

failure indicates that a power failure has occurred, whereas a

RAM check or signature validation indicates that a Watchdog 1

timeout has occurred.

Table 10 shows the possible watchdog decoded statuses.

Table 10. Watchdog Status Decoding

WSTAT

RAM Checksum

Reset Origin

High

Failed

Power failure

High

Watchdog 1

Low

Don't care

Watchdog 2

NOPOWER APPLIED TO AVIN.

ALL REGULATORS AND SUPERVISORY

TURNED OFF

NO POWER

POR

STANDBY

WSTAT = HIGH

RESET

NORMAL

WSTAT = LOW

AVIN < VUVLO

ALL ENx = LOW

AVIN > VUVLO

TRANSITION

STATE

TRANSITION

STATE

TRANSITION

STATE

END OF POR

WSTAT

TIMEOUT

(tWDCLEAR)

WSTAT = 1

TRANSITION

STATE

ALL REGULATORS AND

SUPERVISOR ACTIVATED

WDOG2

TIMEOUT

(tWD2)

WSTAT = 0

END OF (tPOFF)

PULSE

WDOG1 TIMEOUT

(tWD1)AND

WSTAT TIMEOUT

WSTAT = 1

WDOG1 TIMEOUT

(tWD1)

ALL ENx = HIGH

ACTIVE

POWER OFF

RESET SHORT

AVIN < VUVLO

END OF RESET

PULSE (tRP2)

INTERNAL CIRCUIT BIASED

REGULATORS AND

SUPERVISORY NOT ACTIVATED

AVIN < VUVLO

VMON < VTH

END OF RESET

PULSE (tRP1)

Figure 47. ADP5043 State Flow

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