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AS3977 数据表(PDF) 6 Page - ams AG |
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AS3977 数据表(HTML) 6 Page - ams AG |
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6 / 47 page ![]() www.austriamicrosystems.com/AS3977 Revision 3.6 6 - 47 AS3977 Data Sheet - P i n A s s i g n m e n t s CLK 6 SDI clock XTALIN 7 XTAL oscillator input, DC Level approximately 1 Volt, needs an DC Blocker in case of external clock XTALOUT 8 XTAL oscillator output, DC Level approximately 1 Volt VREGDIG 9 Voltage regulator2 (VRegDig) output, requires a capacitor with nominal 100 nF. VDD 10 Positive Power Pin Positive supply of digital part and voltage regulator2 (VRegDig) DATAIO 11 Digital CMOS level input Pin, SDI data input / output MCCLK 12 Micro controller clock output Digital output with variable driver strength VSS 13 GND Pin Negative supply of digital part Reserved 14 Must be connected to GND VCCPA 15 Positive Power Pin Positive supply of PA and voltage regulator VREGRF 16 Voltage regulator output to feed the RF Amplifier. For optimum performance a capacitor with nominal 1µF and 100 nF is recommended. GND 17 GND Power Pin Negative supply of analogue part (exposed paddle) Table 1. Pin Descriptions Pin Name Pin Number Type Description CLK VDD VDD VDD XTALOUT VDD VREGD IG DATAIO MC CCLK VREGR F VC CPA |
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