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AS3977 数据表(PDF) 19 Page - ams AG |
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AS3977 数据表(HTML) 19 Page - ams AG |
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19 / 47 page ![]() www.austriamicrosystems.com/AS3977 Revision 3.6 19 - 47 AS3977 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 9 Application Information Figure 5. Functional Description Diagram of Timers and Data Synchronization The Prescaler divides the XTAL frequency by fOUT=2 -PSC<2:0>*f IN The Compare timer divides by fOUT=fIN/(TCV+1) and the Postscaler divides the input frequency by fOUT=2 -ASC<1:0>*f IN which leads into a data frequency of: fOUT=2 -(PSC<2:0>+ASC<1:0>+1)* f IN / (TCV+1) (EQ 2) 9.1 Operation Modes All modes are controlled by the SDI interface. Power Down Mode The AS3977 is connected to the power supply and can be switched to power down mode. The current consumption is limited by the leakage current. Clock Enable Mode In this mode, only the reference frequency generator is switched on and a clock signal is supplied via the clock output. PLL Enable Mode The PLL is switched on and locked at the selected output frequency. The power amplifier is in power down mode. This mode enables OOK- ASK modulation by switching the PA on and off. Transmit Mode The PLL is switched on and locked at the selected output frequency. The power amplifier is in power on mode. This is the FSK mode for transmitting data. Baudrate Generator Data Generator Data Synchronization MC TXDO 3 to 1 xor Postscalar / 1,2,4,8 2 ASC 3 PSC 8 timer compare value compare counter 8bit INV Powerdown Timer Powerdown reset reset 2 CLK Source TXDATA MCCLK XTAL ENABLE / 2^16 Set Powerdown Prescalar / 1,2,4,8,… 128 3 to 1 1 |
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