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AS3977

Data Sheet - D e t a i l e d S y s t e m D e s c r i p t i o n

8 Detailed System Description

The AS3977 is based on a fully integrated sigma-delta controlled fractional-N synthesizer phase locked loop (PLL) and a power amplifier (PA). A

reference frequency generator including a crystal oscillator provides the comparison frequency of the PLL and a high-precision clock output. A

programmable Gaussian filter enables to minimize the occupied bandwidth and adjacent channel power. A temperature sensor with digital read-

out is included that allows compensation of the crystal frequency drift due to temperature variation. An on-chip low drop out regulator (LDO) is

available in case an accurate output power independent of supply voltage variation is required. A second LDO for the digital supply voltage helps

to minimize interference between the analog and digital part and decreases the current consumption of the digital part. A PROM enables the

compensation of process variation. The AS3977 is controlled by an external microcontroller via a bi-directional serial digital interface (SDI).

8.1 Reference Frequency Generator

The reference frequency generator consists of a crystal oscillator and frequency divider. The crystal oscillator can be driven externally in case an

external clock frequency is supplied.

8.2 Phase Locked Loop

The PLL is of standard charge pump type. The phase frequency detector is designed such that dead zone problems are avoided. The charge

pump current is programmable. All loop filter components are on-chip, the bandwidth is programmable through the charge pump current. The

differential based voltage controlled oscillator (VCO) has integrated inductors and varactors. The VCO operates at a center frequency around

1.8GHz. To cover the specified frequency range over process variation, the sufficiently wide overall tuning range is split into 16 overlapping

frequency bands. At start up of the PLL, an automatic range select circuit (ARS) selects the proper frequency band. The VCO output frequency

is divided by 2, 4, and 6, which enables to cover output frequencies in the range of 850 – 928 MHZ, 425 – 450 MHz and 300 – 320 MHz,

respectively. A lock detector enables to monitor the PLL lock status.

8.3 Gaussian Filter and Digital Modulator

The programmable sigma-delta modulator controls the output frequency of the PLL. The order of the modulator is programmable (MASH2 or

MASH3). In combination with the programmable Gaussian filter for the data signal, the modulator performs the FSK modulation with

programmable deviation, whereby the Gaussian Filter enables to minimize the occupied bandwidth and the adjacent channel power.

8.4 Power Amplifier

The power amplifier is single ended and consists of a preamplifier and an output stage, both with open collector. The necessary external chokes

can be connected to a LDO in case an accurate output power independent of supply voltage variation is required. The output power is

programmable up to 10dBm.

8.5 Temperature Sensor

The AS3977 includes a temperature sensor to measure the absolute temperature inside the chip. The analog value is converted to a digital value

and can then be read out by the microcontroller in order to control the output frequency and/or the transmission power. The value of the chip

temperature in degree can be obtained using following formula:

Temperature = TS < 9…0 > * 0.19 – 50

(EQ 1)

The temperature sensor can be used to compensate the crystal drift over temperature.

Note:

AS3977 has the same temperature than the crystal only at start up and the temperature will increase immediately thereafter due to self

heating.

Temperature sensor must be used only in the Clock Enable Mode as a stand alone block. It is mandatory to be used with the PLL and Power

Amplifier switched off.

8.6 Low Power Reset

The low power reset (LPR) disables the power amplifier, if the supply voltage falls below the low power threshold.

8.7 Low Drop Out Regulators

In order to avoid stability issues, external capacitors are required. (see Table 1)