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Revision 3.6

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AS3977

Data Sheet - A p p l i c a t i o n I n f o r m a t i o n

9.2.5 Transmitting Data

Command code has to be provided from LSB to MSB and for transmit it is <C0, C1> = “11”. After the command code, further configuration has to

be provided from the MSB to the LSB. Then a bit-stream, the data to be sent, can be transferred from the SDI master by keeping SDI enable

signal to high. No SDI clock is required for data synchronization or the input bit stream.

Each bit of the command and address sections of the frame have to be driven by the SDI master on the SDI clock transfer edge and the SDI

slave on the next SDI clock edge samples it.

The transmission starts as follows:

After the last configuration bit has been sampled, the micro controller has to provide an additional SDI clock edge to activate the output amplifier.

This allows the SDI state machine to switch to the TX status and to activate MCCLK. Then, together with the first TX data bit, the next SDI clock

sampling edge provided by the master starts the transmission itself and powers on the analog output driver.

In case, the MCCLK output is properly configured, the transmission will be stopped by the microcontroller by setting the clock to a high

impedance state and the MCCLK output of the Transceiver became active and takes over the communication of the Interface.

The power amplifier is switched on (if not already on) at the subsequent sampling edge of CLK after receiving the transmit command byte. This

allows to delay the PAON signal, e.g. to enable locking of the PLL in case a channel hop has to be performed.

The following figure (Figure 12) shows an example (sampling falling edge) of the transmit command with MCCLK active during TX. It is important

to note in this mode the sequence of events labelled 1-4 in the diagram, which lead to transmission. This mode allows the baud clock to be

synchronized to the external data. In such a case, the synchronization (A5=1) bit should be set within the transmitter configuration.

Figure 12. Transmit Command with MCCLK Active During Tx (falling edge sampling)

9.3 Transmitter Control States

9.3.1 Power Down State

When the Power Down Mode is entered, the crystal oscillator ends running and two very important bits of the registers are set to their inactive

values:

1. Lock transmit: which is set (1) during PD to forbid any transmission.

2. Setpd: it is reset (0) to avoid a locked Power Down Mode.

When the circuit is in Power Down Mode, the crystal oscillator and all the other analog/digital circuits are OFF. The transmitter interface is the

only supplied circuit and it is sensitive to SDI signals. The current consumption is limited by the leakage current. The configuration registers do

not alter as long as the minimum supply requirements are met. The state can only be left by the rising edge of ENABLE. The state can be

entered either by setting the set power down bit (SETPD) via. SDI communication or by setting ENABLE low for more than 2

(Power Down Timer). When the Power Down Mode is left (by the rising edge of ENABLE), the crystal oscillator is activated.

1

4

3

2

Tx Configuration and pre-configuration for

MCLK set

Tx configuration parameter ready

uController triggers falling edge of CLK after ris-

ing edge of MCLK

Power Amplifier is switched on

Power Amplifier is

switched off or data is sent

continuously

MCLK started synchronous to

internal baud clock

A5

A4

A3

A2

A1

A0

1

1

Data to be sent

DATAIO

MCCLK

CLK

ENABLE