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Revision 3.6

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AS3977

Data Sheet - A p p l i c a t i o n I n f o r m a t i o n

resolution

Δf and without recalculating all the frequency settings. If the crystal error is known, the resulting error

in the output frequency is

also known. The ratio

can then be used to correct the error. In case the crystal error is positive,

has to be subtracted from, in case

the crystal error is negative it has to be added to FRAC<15:0>.

A similar procedure can be performed to calibrate for initial frequency errors. Note that in both cases the resulting value for FRAC<15:0> has to

fulfil the conditions FRAC<15:0> - DF

≥ 0Η and FRAC<15:0> + DF ≤ FFFFH.

9.8.3.2 Gaussian Filter Clock Setting

(EQ 29)

9.9 Baud Rate Generator

The main functionality of the module is to generate clocks with programmed periods. The first action is to change the parameters followed by

starting a transmission.

Changing PSC, TCV, ASC and CLKS parameters

As soon as the crystal oscillator clock is active, pre scaler and after scaler timer configuration parameters are continuously updated from the

SDI registers. To avoid spurious emissions, these synchronized values cannot be immediately used for new clock generation because the

circuit has to take care about current and new clock phase difference. Then, as soon as the phase difference between them is zero, an

enable signal is generated and new values are stored to the final registers that will be used for the normal functionality of the circuit. At this

point the new clock will start without spurious periods.

Starting a transmission

A typical situation is as follows – After start up and configuration, the circuit goes in Power Down Mode. Then a wake up event occurs on the

SDI interface and the internal crystal oscillator starts running (after a setup time). The wake up event is typically a rising edge on the SDI

enable input that samples the SDI data e.g. to the LOW value and this resets the MCCLK frequency to be 1/16 of the oscillator frequency

and makes the clock always active. At this point the micro-controller starts its activity and it can decide to reprogram MCCLK frequency to

the desired value and to the desired behavior. The decision between current and new value will be done synchronously to eliminate any

possible spurious period on MCCLK (mainly if it is used). In any case it can be maintained the new setting between different Power Down

Modes or it can be reset to the default value on the first access to the SDI interface when the circuit is in Power Down Mode.

9.10 Reference Design PREOUT and PAOUT Connection

For all RF Specification, refer to the Reference Design. The PAOUT pin is Power Line matched to 50

Ω load wherein a power of

8dBm@315MHz/433MHz and 4dBm@868MHz/915MHz is spent typically.

9.10.1 Matching Circuit and PREOUT and PAOUT Connections to the Supply Voltage

Figure 13 shows the Power Line Matching and Transformation Network used on the Reference Design. Table 25 gives the values for several

settings, varying the operation frequency and the Supply Voltage source. Supply blocking capacitors are not shown in the schematic (see Figure

13).

ε

RF

ε

RF

Δf

-----------

ε

RF

Δf

-----------

1

0

:

7

GFCS

+

>

<

=

REF

GF

f

f