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AS3977 数据表(PDF) 27 Page - ams AG |
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AS3977 数据表(HTML) 27 Page - ams AG |
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27 / 47 page ![]() www.austriamicrosystems.com/AS3977 Revision 3.6 27 - 47 AS3977 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 9.4 ENABLE Signal Functionality Figure 21 summarizes the function of ENABLE in combination with the SDI state and the logical level of CLK and DATAIO. Table 21. ENABLE Signal Functionality State ENABLE CLK DATAIO Description Power Down Mode ↑ XX resets the SDI and state machine activates the crystal oscillator (PD is set to low) sets the lock transmit bit 0 X indicates data are sampled at the falling edge of CLK 1 X indicates data are sampled at the rising edge of CLK X0 activates MCCLK, fMCCLK=fXOSC/16 X 1 MCCLK configuration is unchanged All ↑ XX resets the Power Down Timer resets the SDI Interface (re-)enters the Active state Active, Transmit ↓ XX activates the Power Down Timer; after 2 16 crystal clock cycles the IC reaches the Power Down Mode Active, Transmit X X indicates the end of Read/Write (duration: min > 1 SDI CLK cycle, max: < 1/fcrystal * 2 16) All 0 X X disables CLK and DATAIO sets DATAIO to high impedance Transmit ↓ XX switches off the PA (if enabled) latches DATAIO (if enabled) |
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