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STM32F373VC 数据表(PDF) 15 Page - STMicroelectronics

部件名 STM32F373VC
功能描述  ARM® Cortex®-M4 32b MCUFPU, up to 256KB Flash32KB SRAM, timers, 4 ADCs (16-bit Sig. Delta / 12-bit SAR), 3 DACs, 2 comp., 2.0-3.6 V
PDF  137 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F373VC 数据表(HTML) 15 Page - STMicroelectronics

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STM32F373xx
Functional overview
47
3.7
Power management
3.7.1
Power supply schemes
VDD: external power supply for I/Os and the internal regulator. It is provided externally
through VDD pins, and can be 2.0 to 3.6 V.
VDDA = 2.0 to 3.6 V:
external analog power supplies for Reset blocks, RCs and PLL
supply voltage for 12-bit ADC, DACs and comparators (minimum voltage to be
applied to VDDA is 2.4 V when the 12-bit ADC and DAC are used).
VDDSD12 and VDDSD3 = 2.2 to 3.6 V: supply voltages for SDADC1/2 and SDADCD3
sigma delta ADCs. Independent from VDD/VDDA.
VBAT= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers when VDD is not present.
3.7.2
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry.
It is always active, and ensures proper operation starting from/down to 2 V. The device
remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the
need for an external reset circuit. The POR monitors only the VDD supply voltage.
During the startup phase it is required that VDDA should arrive first and be greater than
or equal to VDD.
The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.7.3
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR), and power-down.
The MR mode is used in the nominal regulation mode (Run)
The LPR mode is used in Stop mode.
The power-down mode is used in Standby mode: the regulator output is in high
impedance, and the kernel circuitry is powered down thus inducing zero consumption.
The voltage regulator is always enabled after reset. It is disabled in Standby mode.



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