ADE7933 datasheet(43/125 Pages) AD

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Data Sheet

ADE7978/ADE7933/ADE7932/ADE7923

Rev. D | Page 43 of 125

Voltage Waveform Gain Registers

There is a multiplier in the signal path of each phase voltage.

The voltage waveform can be changed by ±100% by writing

a corresponding twos complement number to the 24-bit signed

voltage waveform gain registers (AVGAIN, AV2GAIN, BVGAIN,

BV2GAIN, CVGAIN, CV2GAIN, NVGAIN, and NV2GAIN).

For example, if 0x400000 is written to these registers, the ADC

output is scaled up by 50%. To scale the output by −50%, write

0xC00000 to the registers. Equation 12 describes mathematically

the function of the voltage waveform gain registers.

Voltage Waveform = ADC Output ×













Gain

Voltage

Contents

(12)

Changing the contents of the AVGAIN, AV2GAIN, BVGAIN,

BV2GAIN, CVGAIN, CV2GAIN, NVGAIN, or NV2GAIN

corresponding phase, including the active, reactive, and apparent

energy and the voltage rms calculations. In addition, waveform

samples scale accordingly.

The serial ports of the ADE7978 work with 32-, 16-, or 8-bit

words, whereas the DSP works with 28-bit words. Like the

xIGAIN registers shown in Figure 52, the AVGAIN, AV2GAIN,

BVGAIN, BV2GAIN, CVGAIN, CV2GAIN, NVGAIN, and

NV2GAIN registers are sign extended to 28 bits and padded

with four 0s for transmission as 32-bit registers.

Voltage Channel HPF

The ADC outputs may contain a dc offset that can create errors

in power and rms calculations. High-pass filters (HPFs) are placed

in the signal path of the phase voltages and the phase and neutral

currents. When the HPF is enabled, the filter eliminates any dc

offset on the voltage channel. All filters in both voltage and current

channels are implemented in the DSP and are enabled by default:

Bit 4 (HPFEN) of the CONFIG register (Address 0xE618) is set

to 1. All filters are disabled by setting Bit 4 (HPFEN) to 0.

Voltage Channel Sampling

The waveform samples of the voltage channels are taken at

the output of the HPF and are stored in the 24-bit signed

VAWV, VA2WV, VBWV, VB2WV, VCWV, VC2WV, VNWV,

and VN2WV registers at a rate of 8 kSPS. All power and rms

calculations remain uninterrupted during this process.

Bit 17 (DREADY) in the STATUS0 register (Address 0xE502) is

set when the VAWV, VA2WV, VBWV, VB2WV, VCWV, VC2WV,

VNWV, and VN2WV registers are available to be read using the

I2C or SPI serial port. Setting Bit 17 (DREADY) in the MASK0

DREADY flag is set. For more information about the DREADY

bit, see the Digital Signal Processor section.

In addition, if Bits[1:0] (ZX_DREADY) in the CONFIG register

are set to 00, the DREADY functionality is selected at the

ZX/DREADY pin. In this case, the pin goes low approximately

70 ns after the DREADY bit is set to 1 in the STATUS0 register.

The ZX/DREADY pin stays low for 10 µs and then returns high.

The low to high transition of the ZX/DREADY pin can be used

to initiate a burst read of the waveform sample registers. For more

information, see the I2C Burst Read Operation and the SPI Burst

Read Operation sections.

For information about using the ZX functionality at the

ZX/DREADY pin (ZX_DREADY bits in the CONFIG register

are set to 01, 10, or 11), see the Zero-Crossing Detection section.

The serial ports of the ADE7978 work with 32-, 16-, or 8-bit

words, whereas the DSP works with 28-bit words. Like the IxWV

registers shown in Figure 53, the 24-bit signed VAWV, VA2WV,

VBWV, VB2WV, VCWV, VC2WV, VNWV, and VN2WV registers

are transmitted as sign extended 32-bit registers.

The ADE7978 contains a high speed data capture (HSDC) port

that is specially designed to provide fast access to the waveform

sample registers. For more information, see the HSDC Interface

section.

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