ADE7933 datasheet(93/125 Pages) AD

93 / 125 page

Data Sheet

ADE7978/ADE7933/ADE7932/ADE7923

Rev. D | Page 93 of 125

Bipolar ac voltage is the most stringent environment. The goal

of a 50-year operating lifetime under the bipolar ac condition

determines the maximum working voltage recommended by

Analog Devices. In the case of dc voltage, the stress on the

insulation is significantly lower. This allows operation at higher

working voltages while still achieving a 50-year service life. The

working voltages listed in Table 13 can be applied while

maintaining the 50-year minimum lifetime, provided that the

voltage conforms to dc voltage cases. Treat any cross-insulation

voltage waveform that does not conform to Figure 119 as a

bipolar ac waveform, and limit its peak voltage to the 50-year

lifetime voltage value listed in Table 13.

LAYOUT GUIDELINES

Figure 42 shows the test circuit of the ADE7978/ADE7933/

ADE7932 and ADE7923 chipset. The test circuit contains three

ADE7933 devices, one ADE7923, and one ADE7978, together

with the circuitry required to sense the phase currents and

voltages in a 3-phase system. The chipset is managed by a

microcontroller (MCU) using the SPI interface. (The MCU is

not shown in the schematic.) Figure 42 replicates the schematic

of the ADE7978/ADE7933 evaluation board (see Figure 120).

A 4-layer PCB is required when using the ADE7978/ADE7933/

ADE7932/ADE7923 chipset. It creates a low noise design with

high immunity to EMC influences. The devices pass Class B

CISPR22/EN-55022 standard specification with a sufficient

margin only with a 4-layer PCB. Figure 120 through Figure 123

show a recommended layout for a printed circuit board (PCB)

with four layers; in this layout, the components are placed only

on the top side of the board. Note that Figure 120 through

Figure 123 show layout images that were cropped from images

of a board containing other circuitry besides the ADE7978,

ADE7933, and ADE7923 devices.

The layout of a meter using the ADE7932 is very similar to

the one designed for the ADE7933. The only difference is the

absence of the Voltage Channel V2 and its related circuitry: the

resistor divider and the protection diodes.

If full isolation is required even from the neutral line, then an

ADE7933/ADE7923 can be used in place of an ADE7923. The

footprint of both devices is the same and the layout is very

similar to the layout pictured in Figure 120 through Figure 123.

Replicate the layout around a ADE7933 from Phase A, B, or C

and replace the layout around the ADE7923 on the neutral line.

This means replicating all four layers of the PCB around phase

A, B, or C for the neutral line. For detailed information on the

layout guidelines to follow, use the AN-1333 Application Note,

Architecting a Direct, 3-Phase Energy Meter with Shunts Using

ADE7932/ADE7933/ADE7978.

The primary supply voltage is supplied at VDD (Pin 19) of the

ADE7933 and ADE7923. Two decoupling capacitors are placed

between VDD and GND (Pin 20): a 10 µF capacitor and a

100 nF ceramic capacitor. The ceramic capacitor must be placed

closest to the ADE7933/ADE7932 and ADE7923 because it

decouples the high frequency noise; the 10 µF capacitor must be

placed in close proximity to the ADE7933/ADE7932. The

ADE7923 VDD pins (Pin 1 and 19) must be connected externally

with two 100 nF ceramic capacitors, each closest to both pins

and one 10 µF capacitor in close proximity to the 100 nF

capacitors. The VDD pins must be externally connected to each

other in the shortest path possible.

The ADE7933 VDDISO pin (Pin 1) is decoupled from GNDISO

(Pin 2) using two capacitors: a 10 µF capacitor and a 100 nF

ceramic capacitor. Place the ceramic capacitor closest to the

ADE7933/ADE7932; place the 10 µF capacitor in close

proximity to the ADE7933/ADE7932.

The ADE7933 LDO and REF pins (Pin 8 and Pin 9) are each

decoupled from GNDISO (Pin 10) using two capacitors: a 4.7 µF

capacitor and a 100 nF ceramic capacitor. In the same way, the

ADE7923 LDO and REF pins (Pin 8 and Pin 9) are each

decoupled from GND (Pin 10) using the same two capacitors.

Place the ceramic capacitor closest to the ADE7933/ADE7932

and ADE7923; place the 4.7 µF capacitor in close proximity to

the ADE7933/ADE7932 and ADE7923.

Note that the ADE7933/ADE7932 isolated ground point is one

of the shunt poles. This point is directly connected to Pin 10

(GNDISO). It is not necessary to connect the shunt ground pole

to Pin 2; the two GNDISO pins (Pin 2 and Pin 10) are internally

connected to each other. The ADE7923 ground point is one of

the shunt poles; this ground is the ground of the MCU because

the ADE7923 is not isolated. Pin 2 and Pin 10 are connected

internally, and Pin 11 and Pin 20 are connected internally. These

two pairs must be connected externally to the same GND on

the board. If isolation is required on the neutral line, an

ADE7933/ADE7923 can be used with the layout copied from a

separate phase to the neutral line.

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