ADE7933 datasheet(47/125 Pages) AD

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Data Sheet

ADE7978/ADE7933/ADE7932/ADE7923

Rev. D | Page 47 of 125

POWER QUALITY MEASUREMENTS

ZERO-CROSSING DETECTION

The ADE7978 has a zero-crossing (ZX) detection circuit on the

phase current and phase voltage channels. The neutral current

datapath and the second voltage channels do not have zero-

crossing detection circuits. Zero-crossing events are used as a

time base for various power quality measurements and in the

calibration process.

The output of the digital filter LPF1 is used to generate zero-

crossing events. The low-pass filter is intended to eliminate all

harmonics of 50 Hz and 60 Hz systems and to help identify

zero-crossing events on the fundamental components of both

current and voltage channels.

LPF1 has a pole at 80 Hz and is clocked at 256 kHz. As a result,

there is a phase lag between the analog input signal (one of IA,

IB, IC, VA, VB, or VC) and the output of LPF1. The error in ZX

detection is 0.0703° for 50 Hz systems and 0.0843° for 60 Hz

systems. The phase lag response of LPF1 results in a time delay

of approximately 31.4° (1.74 ms) at 50 Hz between the input

and output. The overall delay between the zero crossing on the

analog inputs and the ZX detection obtained after LPF1 is

approximately 39.6° (2.2 ms) at 50 Hz. The ADC and HPF

introduce the additional delay. To assure a good resolution of

the ZX detection, LPF1 cannot be disabled. Figure 61 shows

how the zero-crossing signal is detected.

IA, IB, IC AFTER

TEMPERATURE

COMPENSATION

VA, VB, VC AFTER

HPF

DETECTION

LPF1

IA, IB, IC,

OR VA, VB, VC

39.6° OR 2.2ms @ 50Hz

0.855

ZX/

DREADY PIN

LPF1

OUTPUT

Figure 61. Zero-Crossing Detection on Voltage and Current Channels

To provide additional protection from noise, input signals to

the voltage channel with amplitudes 1000 times lower than full

scale never generate zero-crossing events. The current channel

ZX detection circuit is active for all input signals, regardless of

their amplitudes.

The ADE7978 contains six zero-crossing detection circuits, one

for each phase voltage and current channel. Each circuit drives a

flag in the STATUS1 register (Address 0xE503). The status bits set

in the STATUS1 register when a zero-crossing detection circuit

detects a zero-crossing event are listed in Table 21.

Table 21. Zero-Crossing Status Bits in the STATUS1 Register

Bit No.

Bit Name

Zero-Crossing Event Detected on

ZXVA

Phase A voltage

ZXVB

Phase B voltage

ZXVC

Phase C voltage

ZXIA

Phase A current

ZXIB

Phase B current

ZXIC

Phase C current

If a ZX detection bit (any of Bits[14:9]) is set in the MASK1 register

(Address 0xE50B), the IRQ1 interrupt pin is driven low and the

corresponding status flag is set to 1 when the configured zero-

crossing event occurs. The status bit is cleared and the IRQ1 pin

returns high when a 1 is written to the appropriate bit in the

STATUS1 register.

By default, the ZX/DREADY pin is configured for the DREADY

functionality. Zero-crossing functionality can be configured for

the ZX/DREADY pin by setting Bits[1:0] (ZX_DREADY) in the

CONFIG register (Address 0xE618). When the ZX/DREADY pin

is configured for the ZX function, the pin stays high when the

phase voltage is positive and goes low when the phase voltage is

negative (see Figure 61).

When the ZX_DREADY bits are set to 01, zero-crossing events

detected on the Phase A voltage trigger the ZX/DREADY pin to

toggle simultaneously with Bit 9 (ZXVA) in the STATUS1 register

being set to 1. When the ZX_DREADY bits are set to 10 or 11,

zero-crossing events detected on the Phase B or Phase C voltage

trigger the ZX/DREADY pin to toggle simultaneously with Bit 10

(ZXVB) or Bit 11 (ZXVC) in the STATUS1 register being set to 1.

Zero-Crossing Timeout

Each zero-crossing detection circuit has an associated internal

timeout register that starts to decrement 1 ms (sixteen cycles of

a 16 kHz clock) after a zero-crossing event is triggered. This

62.5 µs (16 kHz clock). The register is reset to the ZXTOUT value

every time a zero crossing is detected. The default value of this

a zero crossing is detected, one of Bits[8:3] of the STATUS1

•

Bit 3 (ZXTOVA), Bit 4 (ZXTOVB), and Bit 5 (ZXTOVC)

in the STATUS1 register refer to the Phase A, Phase B, and

Phase C voltage channels.

•

Bit 6 (ZXTOIA), Bit 7 (ZXTOIB), and Bit 8 (ZXTOIC) in

the STATUS1 register refer to the Phase A, Phase B, and

Phase C current channels.

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