ADE7933 datasheet(62/125 Pages) AD

62 / 125 page

ADE7978/ADE7933/ADE7932/ADE7923

Data Sheet

Rev. D | Page 62 of 125

Phase A, Phase B, and Phase C zero crossings are included

when counting the number of half line cycles by setting

Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combi-

nation of zero crossings from all three phases can be used to

count the zero crossings. Select only one phase at a time for

inclusion in the count of zero crossings during calibration.

The number of zero crossings is specified by the 16-bit

unsigned LINECYC register. The ADE7978 can accumulate

active power for up to 65,535 combined zero crossings. Note

that the internal zero-crossing counter is always active. By

setting Bit 0 (LWATT) in the LCYCMODE register, the first

energy accumulation result is, therefore, incorrect. Writing to

the LINECYC register when the LWATT bit is set resets the

zero-crossing counter, thus ensuring that the first energy

accumulation result is accurate.

At the end of an energy calibration cycle, Bit 5 (LENERGY) in

the STATUS0 register is set. When the corresponding mask bit

in the MASK0 register is enabled, the IRQ0 pin is set low. The

status bit is cleared and the IRQ0 pin is returned high by writing

a 1 to Bit 5 (LENERGY) in the STATUS0 register.

Because the active power is integrated on an integer number of

half line cycles in line cycle accumulation mode, the sinusoidal

components are reduced to 0, eliminating any ripple in the

energy calculation. Therefore, total energy accumulated using

the line cycle accumulation mode is

cos(φk − γk)

(34)

where nT is the accumulation time.

Note that line cycle active energy accumulation uses the same

signal path as active energy accumulation. The LSB size of these

two methods is equivalent.

ADE7933 数据表(PDF) 62 Page - Analog Devices