ADE7933 datasheet(52/125 Pages) AD

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ADE7978/ADE7933/ADE7932/ADE7923

Data Sheet

Rev. D | Page 52 of 125

The maximum absolute value of Phase B is greatest during the

second PEAKCYC period; therefore, the maximum absolute value

is written to the least significant 24 bits of the IPEAK register,

and Bit 25 (IPPHASE[1]) in the IPEAK register is set to 1 at the

end of the period.

At the end of the peak detection period in the current channel,

Bit 23 (PKI) in the STATUS1 register is set to 1; if Bit 23 (PKI)

in the MASK1 register is set, the IRQ1 interrupt pin is driven

low at the end of the PEAKCYC period. In a similar way, at the

end of the peak detection period in the voltage channel, Bit 24

(PKV) in the STATUS1 register is set to 1; if Bit 24 (PKV) in the

MASK1 register is set, the IRQ1 interrupt pin is driven low at the

end of the PEAKCYC period. To identify the phase that triggered

the interrupt, the IPEAK or VPEAK register is read immediately

after reading the STATUS1 register. After identifying the phase

that triggered the interrupt, the status bits are cleared and the

IRQ1 pin is returned high by writing a 1 to Bit 23 (PKI) or Bit 24

(PKV) in the STATUS1 register.

Note that the internal zero-crossing counter is always active.

When Bits[4:2] (PEAKSEL[2:0]) are set in the MMODE register,

the first peak detection result is, therefore, not executed across a

full PEAKCYC period. Writing to the PEAKCYC register when

the PEAKSEL[2:0] bits are already initialized resets the zero-

crossing counter, thereby ensuring that the first peak detection

result is obtained across a full PEAKCYC period.

OVERVOLTAGE AND OVERCURRENT DETECTION

The ADE7978 detects when the instantaneous absolute value

measured on the phase voltage and current channels becomes

greater than the thresholds set in the 24-bit unsigned OVLVL

and OILVL registers (Address 0xE508 and Address 0xE507).

Overvoltage Detection

If Bit 18 (OV) in the MASK1 register is set, the IRQ1 interrupt

pin is driven low if an overvoltage event occurs. Two status flags

are set when an overvoltage event occurs: Bit 18 (OV) in the

STATUS1 register and one of Bits[11:9] (OVPHASE[2:0]) in the

PHSTATUS register (Address 0xE600). The OVPHASE[2:0] bits

identify the phase that generated the overvoltage. Bit 18 (OV) in

the STATUS1 register and Bits[11:9] (OVPHASE[2:0]) in the

PHSTATUS register are cleared and the IRQ1 pin is set high by

writing a 1 to Bit 18 (OV) in the STATUS1 register.

Figure 72 shows overvoltage detection in the Phase A voltage.

When the absolute instantaneous value of the voltage goes above

the threshold set in the OVLVL register, Bit 18 (OV) in the

STATUS1 register and Bit 9 (OVPHASE[0]) in the PHSTATUS

Bit 9 (OVPHASE[0]) in the PHSTATUS register are cleared

when a 1 is written to Bit 18 (OV) in the STATUS1 register.

OVLVL[23:0]

BIT 18 (OV) OF

STATUS1

BIT 9 (OVPHASE)

OF PHSTATUS

PHASE A

VOLTAGE CHANNEL

OVERVOLTAGE

DETECTED

STATUS1[18] AND

PHSTATUS[9]

CANCELLED BY A

WRITE OF STATUS1

WITH OV BIT SET.

Figure 72. Overvoltage Detection

The recommended procedure to manage overvoltage events is

as follows:

1. Enable overvoltage interrupts in the MASK1 register by

setting Bit 18 (OV) to 1.

2. When an overvoltage event occurs, the IRQ1 interrupt pin

goes low and Bit 18 (OV) in the STATUS1 register is set to 1.

3. Read the STATUS1 register to verify that Bit 18 is set to 1.

4. Read the PHSTATUS register (Bits[11:9]) to identify the

phase or phases on which the overvoltage event occurred.

5. Write a 1 to Bit 18 (OV) in the STATUS1 register to clear

Bit 18 and Bits[11:9] (OVPHASE[2:0]) of the PHSTATUS

Overcurrent Detection

If Bit 17 (OI) in the MASK1 register is set, the IRQ1 interrupt

pin is driven low when an overcurrent event occurs. Two status

flags are set when an overcurrent event occurs: Bit 17 (OI) in the

STATUS1 register and one of Bits[5:3] (OIPHASE[2:0]) in the

PHSTATUS register. The OIPHASE[2:0] bits identify the phase

that generated the overcurrent. The recommended procedure to

manage overcurrent events is as follows:

1. Enable overcurrent interrupts in the MASK1 register by

setting Bit 17 (OI) to 1.

2. When an overcurrent event occurs, the IRQ1 interrupt pin

goes low and Bit 17 (OI) in the STATUS1 register is set to 1.

3. Read the STATUS1 register to verify that Bit 17 is set to 1.

4. Read the PHSTATUS register (Bits[5:3]) to identify the

phase or phases on which the overcurrent event occurred.

5. Write a 1 to Bit 17 (OI) in the STATUS1 register to clear

Bit 17 and Bits[5:3] (OIPHASE[2:0]) of the PHSTATUS

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