ADE7933 datasheet(74/125 Pages) AD

74 / 125 page

ADE7978/ADE7933/ADE7932/ADE7923

Data Sheet

Rev. D | Page 74 of 125

By default, the TERMSELx[2:0] bits are set to 1, the CF1SEL[2:0]

bits are set to 000, the CF2SEL[2:0] bits are set to 001, and the

CF3SEL[2:0] bits are set to 010. Therefore, the default configuration

for the energy-to-frequency converters is as follows:

•

The CF1 converter produces signals proportional to the

sum of the total active powers on all three phases.

•

The CF2 converter produces signals proportional to the

sum of the total reactive powers on all three phases.

•

The CF3 converter produces signals proportional to the

sum of the apparent powers on all three phases.

ENERGY-TO-FREQUENCY CONVERSION PROCESS

The energy-to-frequency conversion is accomplished in two

stages. The first stage is the same as for the energy accumulation

processes described in the Active Energy Calculation, Reactive

Energy Calculation, and Apparent Energy Calculation sections.

The second stage uses the frequency divider implemented by

the 16-bit unsigned registers CF1DEN, CF2DEN, and CF3DEN

(Address 0xE611 to Address 0xE613). The values of the CFxDEN

registers depend on the meter constant (MC), measured in

impulses/kWh, and how much energy is assigned to one LSB of

the various energy registers (xWATTHR, xVARHR, and so on).

For example, if a derivative of Wh (10n Wh, where n is an integer)

is desired as one LSB of the xWATTHR register, CFxDEN is

calculated using the following equation:

CFxDEN

]

impulses/k

[

103

(50)

The derivative of Wh must be selected to obtain a CFxDEN

active low for only 1 µs. For this reason, do not set the CFxDEN

fractional results; the result of the division must be rounded to

the nearest integer. If CFxDEN is set equal to 0, the ADE7978

considers it to be equal to 1.

The CFx pulse output stays low for 80 ms if the pulse period is

greater than 160 ms (6.25 Hz). If the pulse period is less than

160 ms and CFxDEN is an even number, the duty cycle of the pulse

output is exactly 50%. If the pulse period is less than 160 ms and

CFxDEN is an odd number, the duty cycle of the pulse output is

(1 + 1/CFxDEN) × 50%

The maximum pulse frequency at the CF1, CF2 or CF3 pins

is 68.8 kHz and is obtained on one phase under the following

conditions:

•

WTHR, VARTHR, and VATHR registers are set to 3.

•

CF1DEN, CF2DEN, and CF3DEN registers are set to 1.

•

Phase is supplied with in-phase full-scale currents and

voltages.

The CFx pulse output is active low. It is recommended that the

pin be connected to an LED, as shown in Figure 93. No transistor

is required to supplement the drive strength of the CFx pin.

VDD

CFx

Figure 93. CFx Pin Recommended Connection

Bits[11:9] (CF3DIS, CF2DIS, and CF1DIS) of the CFMODE

converter output is generated at the CF3, CF2, or CF1 pin. When

Bit CFxDIS is set to 1 (the default value), the CFx pin is disabled

and the pin stays high. When Bit CFxDIS is cleared to 0, the

corresponding CFx pin output generates an active low signal.

Bits[16:14] (CF3, CF2, and CF1) in the MASK0 register

(Address 0xE50A) manage the CF3, CF2, and CF1 interrupts.

If the CFx bits are set and a high to low transition at the

corresponding frequency converter output occurs, the IRQ0

interrupt is triggered and the appropriate bit in the STATUS0

outputs are not enabled by the CFxDIS bits in the CFMODE

SYNCHRONIZING ENERGY REGISTERS WITH THE

CFx OUTPUTS

The ADE7978 allows the contents of the phase energy

accumulation registers to be synchronized with the generation

of a CFx pulse. When a high to low transition at one frequency

converter output occurs, the contents of all internal phase

energy registers that relate to the power being output at the CFx

pin are latched into the hour registers and then reset to 0. See

Table 30 for the list of registers that are latched based on the

CFxSEL[2:0] bits in the CFMODE register. All three phase

registers are latched independent of the setting of the

TERMSELx[2:0] bits of the COMPMODE register. Figure 94

shows this process for CF1SEL[2:0] = 010 (apparent powers

contribute at the CF1 pin) and CFCYC = 2.

CFCYC = 2

AVAHR, BVAHR,

CVAHR LATCHED

ENERGY REGISTERS

RESET

AVAHR, BVAHR,

CVAHR LATCHED

ENERGY REGISTERS

RESET

CF1 PULSE

BASED ON

PHASE A AND

PHASE B

APPARENT

POWERS

Figure 94. Synchronizing AVAHR and BVAHR with CF1

The 8-bit unsigned CFCYC register (Address 0xE705) contains

the number of high to low transitions at the frequency converter

output between two consecutive latches. Avoid writing a new

value to the CFCYC register during a high to low transition at

any CFx pin.

Bits[14:12] (CF3LATCH, CF2LATCH, and CF1LATCH) of the

CFMODE register enable the latching of the phase energy

accumulation registers when the bits are set to 1. When these

bits are cleared to 0 (the default state), no latching occurs. The

latching process can be used even if the CFx outputs are not

enabled by the CFxDIS bits in the CFMODE register.

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