ADE7933 datasheet(99/125 Pages) AD

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Data Sheet

ADE7978/ADE7933/ADE7932/ADE7923

Rev. D | Page 99 of 125

I2C Burst Read Operation

The registers from Address 0xE50C to Address 0xE526

represent quantities computed by the ADE7978 every 8 kHz.

These registers contain the following information:

•

Waveform samples (IAWV, IBWV, ICWV, INWV, VAWV,

VBWV, VCWV, VA2WV, VB2WV, VC2WV, VNWV, and

VN2WV)

•

Instantaneous values of various powers (AWATT, BWATT,

CWATT, AVAR, BVAR, CVAR, AVA, BVA, and CVA)

•

Total harmonic distortion (AVTHD, AITHD, BVTHD,

BITHD, CVTHD, and CITHD)

These registers can be read in two ways: one register at a time

(see the I2C Read Operation section) or multiple consecutive

registers at a time in burst mode.

Burst mode is accomplished in two stages (see Figure 127).

The first stage sets the pointer to the address of the first register

in the burst and is identical to the first stage executed when only

one register is read. Any register from Address 0xE50C to

Address 0xE526 can be the first register in the burst.

The second stage reads the contents of the registers. The second

stage proceeds as follows (see Figure 127):

1. The master generates a new start condition followed by an

address byte equal to the address byte used when a single

2. After the address byte is received, the ADE7978 acknowledges

the byte and sends the value of the first register located at the

pointer. The register is sent with the most significant byte

first, and all bytes are sent with the most significant bit first.

3. After every eight bits are received, the master generates an

acknowledge.

4. After the bytes of the first register are sent, if the master

acknowledges the last byte, the ADE7978 increments the

pointer by one location to position it at the next register and

begins to send it out byte by byte, most significant byte first.

5. If the master acknowledges the last byte of the second

begins to send data from the next register.

6. The process continues until the master does not acknowledge

the last byte of a register and then generates a stop

condition.

Address 0xE526 is the last location of the memory range allocated

to the burst read operation. Do not perform a burst read operation

on register locations with addresses greater than 0xE526.

The high to low transition of the ZX/DREADY pin can be used

to initiate a burst read operation. The pin must be configured for

the DREADY functionality (set Bits[1:0], ZX_DREADY, to 00

in the CONFIG register, Address 0xE618). The ZX/DREADY

pin goes low approximately 70 ns after Bit 17 (DREADY) in the

STATUS0 register (Address 0xE502) is set to 1. The pin stays

low for 10 µs and then goes high again.

ACK GENERATED

BY ADE7978

ACK

GENERATED BY

MASTER

S 0

SLAVE ADDRESS

MOST SIGNIFICANT

8 BITS OF REGISTER

ADDRESS

LEAST SIGNIFICANT

8 BITS OF REGISTER

ADDRESS

1 1 1 0 0 0 0

BYTE 3

(MOST SIGNIFICANT)

OF REGISTER 0

BYTE 0

(LEAST SIGNIFICANT)

OF REGISTER 0

BYTE 3

(MOST SIGNIFICANT)

OF REGISTER 1

BYTE 0

(LEAST SIGNIFICANT)

OF REGISTER n

SLAVE ADDRESS

ACK GENERATED

BY ADE7978

Figure 127. I2C Burst Read of Consecutive Registers Located Between Address 0xE50C and Address 0xE526

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