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ADE7933 数据表(PDF) 103 Page - Analog Devices

部件名 ADE7933
功能描述  Isolated Energy Metering Chipset for Polyphase Shunt Meters
PDF  125 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7933 数据表(HTML) 103 Page - Analog Devices

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Data Sheet
ADE7978/ADE7933/ADE7932/ADE7923
Rev. D | Page 103 of 125
Table 60 describes the HCLK, HSIZE, HGAP, HXFER[1:0], and
HSAPOL bits in the HSDC_CFG register. Table 38 lists the time
it takes to execute an HSDC data transfer for all HSDC_CFG
register settings. For some settings, the transfer time is less than
125 µs (8 kHz), which is the update rate of the waveform sample
registers. When the transfer time is less than 125 µs, the HSDC
port transmits data every sampling cycle. When the transfer
time is greater than 125 µs, the HSDC port transmits data only
in the first of two consecutive 8 kHz sampling cycles; that is, the
port transmits registers at an effective rate of 4 kHz.
Table 38. Communication Times for Various HSDC Settings
HXFER[1:0]
HGAP
HSIZE1
HCLK
Communication Time (µs)
00
0
N/A
0
64
00
0
N/A
1
128
00
1
0
0
77.125
00
1
0
1
154.25
00
1
1
0
119.25
00
1
1
1
238.25
01
0
N/A
0
28
01
0
N/A
1
56
01
1
0
0
33.25
01
1
0
1
66.5
01
1
1
0
51.625
01
1
1
1
103.25
10
0
N/A
0
36
10
0
N/A
1
72
10
1
0
0
43
10
1
0
1
86
10
1
1
0
66.625
10
1
1
1
133.25
1 N/A means not applicable.
HSCLK
HSD
HSA
IAVW (32 BITS)
31
0
VAWV (32 BITS)
31
0
IBWV (32 BITS)
31
0
CFVAR (32 BITS)
31
0
Figure 133. HSDC Communication for HGAP = 0, HXFER[1:0] = 00, and HSAPOL = 0; HSIZE Is Irrelevant
HSCLK
HSD
HSA
IAVW (32 BITS)
31
0
VAWV (32 BITS)
31
0
IBWV (32 BITS)
31
0
CVAR (32 BITS)
31
0
7 HCLK
CYCLES
7 HCLK
CYCLES
Figure 134. HSDC Communication for HSIZE = 0, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0
HSCLK
HSD
HSA
IAVW (BYTE 3)
31
24
IAVW (BYTE 2)
23
16
IAVW (BYTE 1)
15
8
CVAR (BYTE 0)
7
0
7 HCLK
CYCLES
7 HCLK
CYCLES
Figure 135. HSDC Communication for HSIZE = 1, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0



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