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ADN8834ACPZ-R2 数据表(PDF) 4 Page - Analog Devices

部件名 ADN8834ACPZ-R2
功能描述  Ultracompact, 1.5 A Thermoelectric Cooler (TEC) Controller
PDF  27 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADN8834ACPZ-R2 数据表(HTML) 4 Page - Analog Devices

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ADN8834
Data Sheet
Rev. B | Page 4 of 27
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
N-MOSFET
R
DS_NS(ON)
WLCSP, V
PVIN = 5.0 V
40
60
mΩ
WLCSP, V
PVIN = 3.3 V
45
65
mΩ
LFCSP, V
PVIN = 5.0 V
45
75
mΩ
LFCSP, V
PVIN = 3.3 V
55
85
mΩ
Leakage Current
P-MOSFET
I
SW_P_LKG
0.1
10
µA
N-MOSFET
I
SW_N_LKG
0.1
10
µA
SW Node Rise Time1
t
SW_R
C
SW = 1 nF
1
ns
PWM Duty Cycle2
D
SW
6
93
%
SFB Input Bias Current
I
SFB
1
2
µA
PWM OSCILLATOR
Internal Oscillator Frequency
f
OSC
EN/SY high
1.85
2.0
2.15
MHz
EN/SY Input Voltage
Low
V
EN/SY_ILOW
0.8
V
High
V
EN/SY_IHIGH
2.1
V
External Synchronization Frequency
f
SYNC
1.85
3.25
MHz
Synchronization Pulse Duty Cycle
D
SYNC
10
90
%
EN/SY Rising to PWM Rising Delay
t
SYNC_PWM
50
ns
EN/SY to PWM Lock Time
t
SY_LOCK
Number of SYNC cycles
10
Cycles
EN/SY Input Current
I
EN/SY
0.3
0.5
µA
Pull-Down Current
0.3
0.5
µA
ERROR/COMPENSATION AMPLIFIERS
Input Offset Voltage
V
OS1
V
CM1 = 1.5 V, VOS1 = VIN1P − VIN1N
10
100
µV
V
OS2
V
CM2 = 1.5 V, VOS2 = VIN2P − VIN2N
10
100
µV
Input Voltage Range
V
CM1, VCM2
0
V
VDD
V
Common-Mode Rejection Ratio (CMRR)
CMRR
1, CMRR2
V
CM1, VCM2 = 0.2 V to VVDD − 0.2 V
120
dB
Output Voltage
High
V
OH1, VOH2
V
VDD −
0.04
V
Low
V
OL1, VOL2
10
mV
Power Supply Rejection Ratio (PSRR)
PSRR
1, PSRR2
120
dB
Output Current
I
OUT1, IOUT2
Sourcing and sinking
5
mA
Gain Bandwidth Product1
GBW
1, GBW2
V
OUT1,VOUT2 = 0.5 V to VVDD − 1 V
2
MHz
TEC CURRENT LIMIT
ILIM Input Voltage Range
Cooling
V
ILIMC
1.3
V
VREF −
0.2
V
Heating
V
ILIMH
0.2
1.2
V
Current-Limit Threshold
Cooling
V
ILIMC_TH
V
ITEC = 0.5 V
1.98
2.0
2.02
V
Heating
V
ILIMH_TH
V
ITEC = 2 V
0.48
0.5
0.52
V
ILIM Input Current
Heating
I
ILIMH
−0.2
+0.2
µA
Cooling
I
ILIMC
Sourcing current
37.5
40
42.5
µA
Cooling to Heating Current Detection
Threshold
I
COOL_HEAT_TH
40
mA
TEC VOLTAGE LIMIT
Voltage Limit Gain
A
VLIM
(V
DRL − VSFB)/VVLIM
2
V/V
VLIM/SD Input Voltage Range1
V
VLIM
0.2
V
VDD/2
V
VLIM/SD Input Current
Cooling
I
ILIMC
V
OUT2 < VVREF/2
−0.2
+0.2
µA
Heating
I
ILIMH
V
OUT2 > VVREF/2, sinking current
8
10
12.2
µA



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