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ADN8834ACPZ-R2 数据表(PDF) 24 Page - Analog Devices |
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ADN8834ACPZ-R2 数据表(HTML) 24 Page - Analog Devices |
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24 / 27 page  ADN8834 Data Sheet Rev. B | Page 24 of 27 Linear Power Stage Layout Guidelines The linear power stage consists of a MOSFET pair that forms a linear amplifier, which operates in linear mode for very low output currents, and changes to fully enhanced mode for greater output currents. Because the linear power stage does not switch currents rapidly like the PWM power stage, it does not generate noise currents. However, the linear power stage still requires a minimum amount of bypass capacitance to decouple its input. Place a 100 nF capacitor that connects from PVIN to PGNDL as close as possible to the PVIN pin. Placing the Thermistor Amplifier and PID Components The thermistor conditioning and PID compensation amplifiers work with very small signals and have gain; therefore, attention must be paid when placing the external components with these circuits. Place the thermistor conditioning and PID circuit components close to each other near the inputs of Chopper 1 and Chopper 2. Avoid crossing paths between the amplifier circuits and the power stages to prevent noise pickup on the sensitive nodes. Always reference the thermistor to AGND to have the cleanest connection to the amplifier input and to avoid any noise or offset build up. EXAMPLE PCB LAYOUT USING TWO LAYERS Figure 41, Figure 42, and Figure 43 show an example ADN8834 PCB layout that uses two layers. This layout example achieves a small solution size of approximately 20 mm2 with all of the conditioning circuitry and PID included. Using more layers and blinds via allows the solution size to be reduced even further because more of the discrete components can relocate to the bottom side of the PCB. ITEC VTEC PGND TEMPSET VIN TEC+ TEC– NTC CONNECT TO GROUND PLANE CONNECT TO GROUND PLANE CSW_OUT 0402 CIN_S CIN_L RC2 0201 RC1 0201 RV2 0201 RV1 0201 RB 0201 RA 0201 R 0201 RX 0201 CVREF 0201 CI 0402 CF 0201 CD 0201 RI 0201 RP 0201 CVDD RBP PGNDL PGNDL OUT 1 IN 1P IN 2P LDR LDR IN 1N IN 2N VLIM / SD PVIN PVIN ITEC OUT 2 ILIM SW SW VTEC EN /SY VDD PGNDS PGNDS SFB AGND VREF CIN_S CIN_L CVDD P NDL PGNDL P N L PGNDL OUT UT 1 IN N 1 1P IN N 2 2P L L L R R L L LD LD L LDR DR R DR N IN 1 1 1N IN N N 2 2 2 2N VLIM IM / SD SD VI PVIN VI VI PVIN EC TEC ITEC OUT OUT UT UT 2 2 ILIM LIM SW SW W S S S S SW S S SW SW W SW V VTE TE VTEC EN N//SY SY DD VDD D VD P P P P P N PGN N N N N GN NDS NDS S DS S PGN PG S NDS N S S P P P P P PGN GN GN ND NDS DS S S P PGN P NDS N S S S P SFB SFB AGND GN EF V VR RE RE CONNECT AGND TO PGNDS ONLY AT A SINGLE POINT AS A STAR CONNECTION AGND 4.0 3.5 3.0 2.5 1.5 1.0 0.5 0 2.0 Figure 41. Example PCB Layout Using Two Layers (Top and Bottom Layers) |
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