ADE7912 datasheet(39/41 Pages) AD

39 / 41 page

Data Sheet

ADE7912/ADE7913

Rev. C| Page 39 of 41

Table 15. CONFIG Register (Address 0x8)

Bit Location

Bit Name

Default Value

Description

CLKOUT_EN

Enables CLKOUT functionality at the CLKOUT/DREADY pin. When CLKOUT_EN = 0,

the default value, DREADY functionality is enabled. When CLKOUT_EN = 1, CLKOUT

functionality is enabled.

Reserved

Reserved. This bit does not manage any functionality.

PWRDWN_EN

Shuts down the dc-to-dc converter. When PWRDWN_EN = 0, the default value, the

dc-to-dc converter is functional and the Σ-Δ modulators are active. When

PWRDWN_EN = 1, the dc-to-dc converter is turned off and the Σ-Δ modulators are

shut down.

TEMP_EN

This bit selects the second voltage channel measurement. When the TEMP_EN bit is

set to 0, the default value, the voltage between the V2P and VM pins is measured.

When this bit is 1, the internal temperature sensor is measured (see the

Temperature Sensor section for more information). In the case of the ADE7912, the

internal temperature sensor is always measured, and this bit does not have any

significance.

5:4

ADC_FREQ

These bits select the ADC output frequency.

00 = 8 kHz, 125 µs period.

01 = 4 kHz, 250 µs period.

10 = 2 kHz, 500 µs period.

11 = 1 kHz, 1 ms period.

SWRST

When this bit is set to 1, a software reset is initiated. This bit clears itself to 0 after

one CLKIN cycle.

Selects the bandwidth of the digital low-pass filter of the ADC. When BW = 0, the

default value, the bandwidth is 3.3 kHz. When BW = 1, the bandwidth is 2 kHz. The

bandwidth data is for CLKIN = 4.096 MHz and an ADC output frequency of 8 kHz.

See the Analog-to-Digital Conversion section for details on how CLKIN and the ADC

output frequency influence the bandwidth selection.

Table 16. STATUS0 Register (Address 0x9)

Bit Location

Bit Name

Default Value

Description

RESET_ON

During reset, the RESET_ON bit is set to 1. When the reset ends and the

ADE7912/ADE7913 are ready to be configured, the RESET_ON bit is cleared to 0.

CRC_STAT

If the CRC of the configuration registers changes value, CRC_STAT bit is set to 1.

IC_PROT

If the configuration registers are not protected, this bit is 0. After the configuration

registers are protected (lock register = 0xCA), this bit is set to 1.

7:3

Reserved

Reserved. These bits do not represent any functionality.

Table 17. Lock Register (Address 0xA)

Bit Location

Bit Name

Default Value

Description

7:0

LOCK_KEY

00000000

When the LOCK_KEY bits are equal to 0xCA, protection of the configuration

registers is enabled. When the LOCK_KEY bits are equal to 0x9C, the protection is

disabled and the configuration registers can be written.

This is a write only register. If the address location is read, the value is 0x00.

Table 18. SYNC_SNAP Register (Address 0xB)

Bit Location

Bit Name

Default Value

Description

Sync

When the sync bit is set to 1 via a broadcast SPI write operation, the

ADE7912/ADE7913 devices in the system generate ADC outputs in the same exact

moment. The bit clears itself back to 0 after one CLKIN cycle. See the Synchronizing

Multiple ADE7912/ADE7913 Devices section for more details.

Snap

When the snap bit is set to 1 via a broadcast SPI write operation, the internal

counters of the ADE7912/ADE7913 devices in the system are latched. The bit clears

itself back to 0 after one CLKIN cycle. See the Synchronizing Multiple

ADE7912/ADE7913 Devices section for more details.

7:2

Reserved

Reserved. These bits do not represent any functionality.

ADE7912 数据表(PDF) 39 Page - Analog Devices

ADE7912 数据表(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

数据表下载

链接网址

ADE7912 数据表(PDF) 39 Page - Analog Devices

ADE7912 数据表(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

数据表 下载

链接网址

数据表下载