Data Sheet

ADE7912/ADE7913

Rev. C | Page 11 of 41

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADE7912/

ADE7913

TOP VIEW

(Not to Scale)

V2P

3

V1P

4

GND

20

VDD

19

CS

18

SCLK

17

VM

5

MOSI

16

IM

6

MISO

15

IP

7

XTAL2

14

LDO

8

XTAL1

13

REF

9

CLKOUT/DREADY

12

GND

11

Figure 7. Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

Isolated Secondary Side Power Supply. This pin provides access to the 2.8 V on-chip isolated power

supply. Do not connect external load circuitry to this pin. Decouple this pin with a 10 µF capacitor in

2, 10

Ground Reference of the Isolated Secondary Side. These pins provide the ground reference for the

analog circuitry. Use these quiet ground references for all analog circuitry. These two pins are

connected together internally.

3, 4, 5

V2P, V1P, VM

Analog Inputs for the Voltage Channels. The voltage channels are used with the voltage

transducers. V2P and V1P are pseudo differential voltage inputs with a maximum signal level of

±500 mV with respect to VM for specified operation. Use these pins with the related input circuitry,

as shown in Figure 20. If V1P or V2P is not used, connect it to the VM pin. On the ADE7912, connect

the V2P pin to the VM pin because the V2P voltage channel is not available. The second voltage

channel is available on the ADE7913 only.

6, 7

IM, IP

Analog Inputs for the Current Channel. The current channel is used with shunts. IM and IP are

pseudo differential voltage inputs with a maximum differential level of ±31.25 mV. Use these pins

with the related input circuitry, as shown in Figure 20.

8

LDO

2.5 V Output of Analog Low Dropout (LDO) Regulator. Decouple this pin with a 4.7 µF capacitor in

this pin.

9

REF

Voltage Reference. This pin provides access to the on-chip voltage reference. The on-chip reference

with a ceramic 100 nF capacitor.

11, 20

GND

Primary Ground Reference.

12

CLKOUT/DREADY

Clock Output (CLKOUT). When CLKOUT functionality is selected (see the Synchronizing Multiple

ADE7912/ADE7913 Devices section for details), the ADE7912/ADE7913 generate a digital signal

synchronous to the master clock at the XTAL1 pin. Use CLKOUT to provide a clock to other

ADE7912/ADE7913 devices on the board.

Data Ready, Active Low (DREADY). When DREADY functionality is selected (see the Synchronizing

Multiple ADE7912/ADE7913 Devices section for details), the ADE7912/ADE7913 generate an active

low signal synchronous to the ADC output frequency. Use this signal to start reading the ADC

outputs of the ADE7912/ADE7913.

13

XTAL1

Master Clock Input. An external clock can be provided at this logic input. The CLKOUT/DREADY

signal of another appropriately configured ADE7912/ADE7913 (see the Synchronizing Multiple

ADE7912/ADE7913 Devices section for details) can be provided at this pin. Alternatively, a crystal

with a maximum drive level of 0.5 mW and an equivalent series resistance (ESR) of 20 Ω can be

connected across XTAL1 and XTAL2 to provide a clock source for the ADE7912/ADE7913. The clock

frequency for specified operation is 4.096 MHz, but lower frequencies down to 3.6 MHz can be used.

See the ADE7912/ADE7913 Clock section for more details.

14

XTAL2

Crystal, Second Input. A crystal with a maximum drive level of 0.5 mW and an ESR of 20 Ω can be

connected across XTAL2 and XTAL1 to provide a clock source for the ADE7912/ADE7913.

15

MISO

Data Output for SPI Port. Pull up this pin with a 10 kΩ resistor (see the SPI-Compatible Interface

section for details).

16

MOSI

Data Input for SPI Port.