ADE7912 datasheet(20/41 Pages) AD

20 / 41 page

ADE7912/ADE7913

Data Sheet

Rev. C | Page 20 of 41

ADC Transfer Function

All ADCs in the ADE7912/ADE7913 produce 24-bit signed

output codes. With a full-scale input signal of 31.25 mV on the

current channel and 0.5 V on the voltage channels, and with

an internal reference of 1.2 V, the ADC output code is nominally

5,320,000 and usually varies for each ADE7912/ADE7913 around

this value. The code from the ADC can vary between 0x800000

(−8,388,608) and 0x7FFFFF (+8,388,607); this is equivalent to

an input signal level of ±49.27 mV on the current channel and

±0.788 V on the voltage channels. However, for specified

performance, do not exceed the nominal range of ±31.25 mV

for the current channel and ±500 mV for the voltage channels;

ADC performance is guaranteed only for input signals within

these limits. For input signals outside these limits, the digital

low-pass filter of the ADCs (see Figure 25) overflows.

ADC Output Values

The ADC output values are stored in three 24-bit signed

registers, IWV, V1WV, and V2WV, at a rate defined by Bits[5:4]

(ADC_FREQ) in the CONFIG register. The output frequency is

8 kHz (CLKIN/512), 4 kHz (CLKIN/1024), 2 kHz (CLKIN/2048),

or 1 kHz (CLKIN/4096) based on ADC_FREQ being equal to

00, 01, 10, or 11, respectively, when CLKIN is 4.096 MHz.

The microcontroller reads the ADC output registers one at a time

or in burst mode. See the SPI Read Operation section and the

SPI Read Operation in Burst Mode section for more information.

REFERENCE CIRCUIT

The nominal reference voltage at the REF pin is 1.2 V. This

reference voltage is used for the ADCs in the ADE7912/

ADE7913. Because the on-chip dc-to-dc converter cannot

supply external loads, the REF pin cannot be overdriven by

a standalone external voltage reference.

The voltage of the ADE7912/ADE7913 reference drifts slightly

with temperature. Table 1 lists the gain drift over temperature

specification of each ADC channel. This value includes the

temperature variation of the ADC gain, together with the

temperature variation of the internal voltage reference.

CRC OF ADC OUTPUT VALUES

Every output cycle, the ADE7912/ADE7913 compute the cyclic

redundancy check (CRC) of the ADC output values stored in

the IWV, V1WV, and V2WV registers. Bits[5:4] (ADC_FREQ)

in the CONFIG register determine the ADC output frequency

and, therefore, the update rate of the CRC.

The CRC algorithm is based on the CRC-16-CCITT algorithm.

The registers are introduced into a linear feedback shift register

(LFSR) based generator one byte at a time, least significant byte

first, as shown in Figure 28. Each byte is then used with the most

significant bit first. The 16-bit result is written in the ADC_CRC

When Bits[5:4] (ADC_FREQ) in the CONFIG register are set

to 00, the ADC output frequency is 8 kHz and the ADC_CRC

generated during the same ADC output cycle. When ADC_FREQ

bits are set to 01, 10 or 11, the ADC output frequency is 4 kHz,

2 kHz, and 1 kHz, respectively and the ADC_CRC register contains

the CRC of the IWV, V1WV, and V2WV registers generated

during the previous ADC output cycle.

LFSR

GENERATOR

a71

a48 a47

a24 a23

IWV REGISTER

815

V1WV REGISTER

V2WV REGISTER

815

Figure 28. CRC Calculation of ADC Output Values

LFSR

g15

b15

a71, a70,....,a2, a1, a0

Figure 29. LFSR Generator Used for ADC_CRC Calculation

Figure 29 shows how the LFSR works. The IWV, V1WV, and

V2WV registers form the [a71, a70,…, a0] bits used by the LFSR.

Bit a0 is Bit 7 of the first register to enter the LFSR; Bit a71 is

Bit 16 of V2WV, the last register to enter the LFSR. The formulas

that govern the LFSR are as follows:

bi(0) = 1, where i = 0, 1, 2, …, 15, the initial state of the bits that

form the CRC. Bit b0 is the least significant bit, and Bit b15 is the

most significant bit.

gi, where i = 0, 1, 2, …, 15 are the coefficients of the generating

polynomial defined by the CRC-16-CCITT algorithm as

follows:

G(x) = x16 + x12 + x5 + 1

(1)

g0 = g5 = g12 = 1

(2)

All other gi coefficients are equal to 0.

FB(j) = aj − 1 XOR b15(j − 1)

(3)

b0(j) = FB(j) AND g0

(4)

bi(j) = FB(j) AND gi XOR bi − 1(j − 1), i = 1, 2, 3, …, 15

(5)

Equation 3, Equation 4, and Equation 5 must be repeated for j =

1, 2, …, 72. The value written into the ADC_CRC register contains

Bit bi(72), i = 0, 1, …, 15.

The ADC_CRC register can be read by executing an SPI register

read access or as part of the SPI burst mode read operation. See

the SPI Read Operation section and the SPI Read Operation in

Burst Mode section for more details.

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