ADE7912 datasheet(28/41 Pages) AD

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ADE7912/ADE7913

Data Sheet

Rev. C | Page 28 of 41

SYNCHRONIZING MULTIPLE ADE7912/ADE7913

DEVICES

The ADE7912/ADE7913 allow the user to sample all currents

and voltages simultaneously and to provide coherent ADC

output samples, which is a highly desired feature in polyphase

metering systems. The electromagnetic interference (EMI)

reduction scheme managed by the EMI_CTRL register (see

the DC-to-DC Converter section for details) requires that the

ADE7912/ADE7913 provide coherent samples.

The ADE7912/ADE7913 in Polyphase Energy Meters section

describes how a polyphase energy meter containing multiple

ADE7912/ADE7913 devices can use one crystal to clock all the

ADE7912/ADE7913 devices. At power-up, only one ADE7912/

ADE7913 device is clocked from the crystal, as the other devices

are set to receive the clock from the CLKOUT/DREADY pin of

the first ADE7912/ADE7913 device. This pin has DREADY

functionality enabled by default. In Figure 34, Figure 36, and

Figure 37, the ADE7912/ADE7913 device on Phase A is clocked

from the crystal, and the CLKOUT/DREADY pin generates the

DREADY signal. The other ADE7912/ADE7913 devices are

clocked by the DREADY signal because the CLKOUT signal has

not yet been received by their XTAL1 pins. The microcontroller

enables CLKOUT functionality when Bit 0 (CLKOUT_EN) is

set to 1 in the CONFIG register. This operation ensures that the

other ADE7912/ADE7913 devices in the system receive the same

clock as the ADE7912/ADE7913 on Phase A and that all ADCs

within all ADE7912/ADE7913 devices in the system sample

data at the same exact moment.

As an alternative to using one crystal, the microcontroller can

generate a clock signal to the XTAL1 pins of every ADE7912/

ADE7913, ensuring precise ADC sampling synchronization

(see Figure 35).

To configure all ADE7912/ADE7913 devices in an energy meter

to provide coherent ADC output samples, that is, samples obtained

in the same output cycle, all ADE7912/ADE7913 devices must

have the same ADC output frequency and the outputs must be

synchronized. Bits[5:4] (ADC_FREQ) in the CONFIG register

select the ADC output frequency; therefore, they must be

initialized to the same value (see the ADC Output Values

section for more details).

To synchronize the ADC outputs, that is, to set all ADE7912/

ADE7913 devices to generate ADC outputs at the same exact

moment (after power-up), the microcontroller must broadcast a

write to the 8-bit SYNC_SNAP register with the value 0x01. All

ADE7912/ADE7913 devices then start a new ADC output period

simultaneously when Bit 0 (sync) of the SYNC_SNAP register is

written. The sync bit clears itself to 0 after one CLKIN cycle.

As shown in Figure 34, Figure 36, and Figure 37, the CLKOUT/

DREADY pin of one ADE7912/ADE7913 is connected to an

I/O input of the microcontroller. This ADE7912/ADE7913

device has Bit 0 (CLKOUT_EN) in the CONFIG register set to

the default value, 0, to enable the DREADY functionality. When

the ADC output period starts, the CLKOUT/DREADY pin goes

low for 64 CLKIN cycles (15.625 µs when CLKIN = 4.096 MHz),

signaling that all ADC outputs from all ADE7912/ADE7913

devices are available and the microcontroller must start reading

them. It is recommended that the SPI read in burst mode ensure

that all data is read in the shortest amount of time.

The ADE7912/ADE7913 contain an internal 12-bit counter that

functions at the CLKIN frequency. The counter is synchronized

with the ADC output period and the CLKOUT/DREADY pin.

When a new output period starts, the counter starts decreasing

from a value determined by Bits[5:4] (ADC_FREQ) in the

CONFIG register. Table 12 shows these values.

Table 12. Counter Initial Values as a Function of

ADC_FREQ Bits

Bits[5:4]

(ADC_FREQ)

in CONFIG

ADC

Output

Frequency

(kHz)

Counter C0

Initial Value

(CLKIN =

4.096 MHz)

Counter C0

Initial Value as

a Function of

CLKIN

511

8000

−

CLKIN

1023

4000

−

CLKIN

2047

2000

−

CLKIN

4095

1000

−

CLKIN

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