ADE7912 datasheet(27/41 Pages) AD

27 / 41 page

Data Sheet

ADE7912/ADE7913

Rev. C | Page 27 of 41

SPI Read Operation

The read operation using the ADE7912/ADE7913 SPI interface

is initiated when the master sets the CS pin low and begins sending

one command byte on the MOSI line. The master places data on

the MOSI line starting with the first high to low transition of SCLK.

The bit composition of the command byte is shown in Table 11.

Bits[1:0] are don’t care bits, and they can have any value. The

examples presented throughout this section show them set to 00.

Bit 2 (READ_EN) determines the type of the operation. For a

read, READ_EN must be set to 1. For a write, READ_EN must

be cleared to 0. Bits[7:3] (ADDR) represent the address of the

The ADE7912/ADE7913 SPI samples data on the low to high

transitions of SCLK. After the ADE7912/ADE7913 device receives

the last bit of the command byte on a low to high transition of

SCLK, it begins to transmit the contents on the MISO line when

the next SCLK high to low transition occurs; thus, the master

can sample the data on a low to high SCLK transition. After the

master receives the last bit, it sets the CS and SCLK lines high

and the communication ends. The data lines, MOSI and MISO,

go into a high impedance state. Figure 40 shows an 8-bit register

read operation; 16-bit and 32-bit registers are read in the same

manner.

Table 11. Command Byte for SPI Read/Write Operations

Bit Location

Bit Name

Description

1:0

Reserved

These bits can have any value.

READ_EN

Set this bit to 1 if an SPI read

operation is executed.

Clear this bit to 0 if an SPI write

operation is executed.

7:3

ADDR

Address of the register to be read

or written.

SPI Read Operation in Burst Mode

All ADE7912/ADE7913 output registers (IWV, V1WV, V2WV,

ADC_CRC, STATUS0, and CNT_SNAPSHOT) can be read in

one of two ways: one register at a time (see the SPI Read Operation

section) or together in burst mode. Burst mode is initiated when

the master sets the CS pin low and begins sending the command

byte (see Table 11) on the MOSI line with Bits[7:3] (ADDR) set

to the IWV register address, 00000. This means a command byte

set to 0x04. The master places data on the MOSI line starting

with the first high to low transition of SCLK. The SPI of the

ADE7912/ADE7913 samples data on the low to high transitions

of SCLK. After the ADE7912/ADE7913 device receives the last

bit of the command byte on a low to high transition of SCLK, it

begins to transmit the 24-bit IWV register on the MISO line

when the next SCLK high to low transition occurs; thus, the

master can sample the data on a low to high SCLK transition.

After the master receives the last bit of the IWV register, the

ADE7912/ADE7913 device sends V1WV, followed by V2WV,

ADC_CRC, STATUS0, and CNT_SNAPSHOT.

The master may set the CS and SCLK lines high at any time to

end the communication. The data lines, MOSI and MISO, go

into a high impedance state. See Figure 41 for details of the SPI

read operation in burst mode.

If a register does not need to be read, for example, the 16-bit

CNT_SNAPSHOT register, the master sets the CS and SCLK

lines high after the STATUS0 register is received.

If the IWV register, for example, is not required, but V1WV

is, set the ADDR bits to the V1WV address, 00001, in the

command byte, and execute the burst mode operation.

SPI Write Operation

The SPI write operation initiates when the master sets the CS

pin low and begins sending one command byte (see Table 11).

Bit 2 (READ_EN) must be cleared to 0. The master places data

on the MOSI line starting with the first high to low transition of

SCLK. The SPI of the ADE7912/ADE7913 samples data on the

low to high transitions of SCLK. Next, the master sends the

8-bit value of the register without losing any SCLK cycles. After

the last bit transmits, at the end of the SCLK cycle, the master

sets the CS and SCLK lines high and the communication ends.

The data lines, MOSI and MISO, go into a high impedance

state. See Figure 42 for details of the SPI write operation.

Note that the SPI write operation can execute 8-bit writes only.

The 16-bit synchronization counter register (composed of

COUNTER0 and COUNTER1) is written by executing the

write operation twice: the less significant byte is written first,

followed by the most significant byte. See the Synchronizing

Multiple ADE7912/ADE7913 Devices section for details on the

functionality controlled by the synchronization counter register.

Because the ADE7912/ADE7913 do not need to acknowledge a

write command in any way, this operation can be broadcast to

multiple ADE7912/ADE7913 devices when the same register

must be initialized with the same value.

After executing a write operation, it is recommended to read

back the register to ensure that it was initialized correctly.

ADE7912 数据表(PDF) 27 Page - Analog Devices

ADE7912 数据表(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

数据表下载