ADE9430 datasheet(34/35 Pages) AD

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Data Sheet

ADE9430

APPLICATIONS INFORMATION

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WAVEFORM BUFFER

The ADE9430 has a waveform buffer comprised of 2048, 32-bit

memory locations.

Continuous resampled waveforms with 1024 points per 10 or 12

line cycles processed by the DSP. The data rate varies with the

line period. The waveform buffer holds approximately 100 ms of

waveform data per channel.

Use the SPI burst read mode to read the waveform buffer contents.

The default value bursts out all the channels in the waveform buffer.

The waveform buffer generates an interrupt on IRQ0 after half the

buffer is full and the last address is filled. The DSP must be on to

use the waveform buffer.

See the ADE9430 Technical Reference Manual for additional infor-

mation.

INTERRUPTS AND EVENTS

The ADE9430 has three pins (IRQ0, IRQ1, and CF4/EVENT/

DREADY) that can be used as interrupts to the host processor. The

IRQ0 and IRQ1 pins go low when an enabled interrupt occurs and

stay low until the event is acknowledged by setting the correspond-

ing status bit in the STATUS0 and STATUS1 registers, respectively.

The bits in the MASK0 and MASK1 registers configure respective

interrupts. The EVENT function, which can multiplex with the CF4

and DREADY options, tracks the state of the enabled signals and

goes low and high with these internal signals. The CF4_CFG bits in

CONFIG1 register set the CF4/EVENT/DREADY pin functionality.

See the ADE9430 Technical Reference Manual for additional infor-

mation.

ACCESSING ON-CHIP DATA

SPI Protocol Overview

The ADE9430 has an SPI-compatible interface, consisting of four

pins: SCLK, MOSI, MISO, and SS. The ADE9430 is always an

SPI subordinate; it never initiates SPI communication. The SPI

is compatible with 16-bit and 32-bit read and write operations.

The maximum serial clock frequency supported by this interface is

20 MHz.

The ADE9430 provides SPI burst read functionality on certain

registers and the waveform buffer that allows multiple registers to

be read after sending one CMD_HDR.

See the ADE9430 Technical Reference Manual for additional infor-

mation.

Figure 54. Command Header, CMD_HDR

The ADE9430 SPI port calculates a 16-bit cyclic redundancy check

(CRC-16) of the data sent out on its MOSI pin so that the integrity

of the data received by the main can be checked. The CRC of

the data sent out on the MOSI pin during the last register read is

offered in a 16-bit register, CRC_SPI, and can be appended to the

SPI read data as part of the SPI transaction.

Additional Communication Verification

Registers

The ADE9430 includes three registers that allow SPI operation

verification. The LAST_CMD (Address 0x4AE), LAST_DATA_16

(Address 0x4AC), and LAST_DATA_32 (Address 0x423) registers

record the received CMD_HDR and the last read or transmitted

data. See the ADE9430 Technical Reference Manual for additional

information.

CRC of Configuration Registers

The configuration register CRC feature in the ADE9430 monitors

certain externally and internally accessible register values. It also

optionally includes 15 registers that are individually selectable in

the CRC_OPTEN register. The result is stored in the CRC_RSLT

monitored registers change the value of the CRC_RSLT register.

See the ADE9430 Technical Reference Manual for additional infor-

mation.

Configuration Lock

The configuration lock feature prevents changes to the ADE9430

configuration. To enable this feature, write 0x3C64 to the

WR_LOCK register. To disable the feature, write 0x4AD1 to the

WR_LOCK register.

To determine whether this feature is active, read the WR_LOCK

disabled.

When this feature is enabled, it prevents writing to addresses from

Address 0x000 to Address 0x073 and Address 0x400 to Address

0x4FE. See the ADE9430 Technical Reference Manual for addition-

al information.

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