Data Sheet

ADE9430

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 10 of 35

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

PULL_HIGH

Pull High. Tie this pin to VDD.

2

DGND

Digital Ground. This pin provides the ground reference for the digital circuitry in the ADE9430. Because the digital return currents

in the ADE9430 are small, it is acceptable to connect this pin to the analog ground plane of the whole system. Connect all grounds

(GND, AGND, DGND, and REFGND) together at one point.

3

DVDDOUT

1.8 V Output of the Digital LDO Regulator. Decouple this pin with a 0.1 µF ceramic capacitor in parallel with a 4.7 µF ceramic

capacitor.

4

PM0

Power Mode Pin 0. PM0, combined with PM1, defines the power mode. For normal operation, ground PM0 and PM1.

5

PM1

Power Mode Pin 1. PM1 combined with PM0, defines the power mode. For normal operation, ground PM0 and PM1.

6

RESET

Reset Input, Active Low. This pin must stay low for at least 1 µs to trigger a hardware reset.

7, 8

IAP, IAN

Analog Inputs, Channel IA. The IAP (positive) and IAN (negative) inputs are fully differential voltage inputs with a maximum

differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.

9, 10

IBP, IBN

Analog Inputs, Channel IB. The IBP (positive) and IBN (negative) inputs are fully differential voltage inputs with a maximum

differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.

11, 12

ICP, ICN

Analog Inputs, Channel IC. The ICP (positive) and ICN (negative) inputs are fully differential voltage inputs with a maximum

differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.

13, 14

INP, INN

Analog Inputs, Channel IN. The INP (positive) and INN (negative) inputs are fully differential voltage inputs with a maximum

differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.

15

REFGND

Ground Reference, Internal Voltage Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point.

16

REF

Voltage Reference. The REF pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

1.25 V. An external reference source of 1.2 V to 1.25 V can also be connected at this pin. In either case, decouple REF to REFGND

with a 0.1 µF ceramic capacitor in parallel with a 4.7 µF ceramic capacitor. After reset, the on-chip reference is enabled. To use the

internal voltage reference with the external circuits, a buffer is required.

17

NC1

No Connection. It is recommended to tie this pin to ground.

18

NC2

No Connection. It is recommended to tie this pin to ground.

19, 20

VAN, VAP

Analog Inputs, Channel VA. The VAP (positive) and VAN (negative) inputs are fully differential voltage inputs with a maximum

differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.

21, 22

VBN, VBP

Analog Inputs, Channel VB. The VBP (positive) and VBN (negative) inputs are fully differential voltage inputs with a maximum

differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.

23, 24

VCN, VCP

Analog Inputs, Channel VC. The VCP (positive) and VCN (negative) inputs are fully differential voltage inputs with a maximum

differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.

25

AVDDOUT

1.9 V Output of the Analog LDO Regulator. Decouple AVDDOUT with a 0.1 µF ceramic capacitor in parallel with a 4.7 µF ceramic

capacitor. Do not connect external active circuitry to this pin.

26

AGND

Analog Ground Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point.