ADE9430 datasheet(27/35 Pages) AD

27 / 35 page

Data Sheet

ADE9430

THEORY OF OPERATION

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Rev. 0 | 27 of 35

Energy Accumulation

The energy is accumulated into a 42-bit signed internal energy

defined number of samples or half line cycles configured by

EGY_TMR_MODE bit in the EP_CFG register. When half line

cycle accumulation is enabled, configure the zero-crossing source

using the ZX_SEL bits in the ZX_LP_SEL register. The number

of samples or half line cycles is set in the EGY_TIME register.

The maximum value of EGY_TIME is 8191d. With full-scale inputs,

the internal register overflows in 13.3 sec. For a 50 Hz signal,

EGY_TIME must be lower than 1329 decimals to prevent overflow

during half line cycle accumulation.

After EGY_TIME + 1 samples or half line cycles, the EGYRDY bit

is set in the STATUS0 register and the energy register is updated.

The data from the internal energy register is added or latched to the

user energy register depending on the EGY_LD_ACCUM bit setting

in the EP_CFG register.

The energy register is signed and is 45 bits wide, split between two

32-bit registers, as shown in Figure 47. The user energy can reset

on a read using the RD_RST_EN bit in the EP_CFG register. With

full-scale inputs, the user energy register overflows in 106.3 sec.

See the ADE9430 Technical Reference Manual for additional infor-

mation.

Figure 47. Internal Energy Register to AWATTHR_HI and AWATTHR_LO

ADE9430 数据表(PDF) 27 Page - Analog Devices