ADE9430 datasheet(28/35 Pages) AD

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Data Sheet

ADE9430

THEORY OF OPERATION

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Rev. 0 | 28 of 35

Power Accumulation

The ADE9430 accumulates the total and fundamental values of

active, reactive, and apparent power for all the three phases

into respective xWATT_ACC and xFWATT_ACC, xVAR_ACC and

xFVAR_ACC, and xVA_ACC, and xFVA_ACC 32-bit signed reg-

isters. The number of samples accumulated is set using the

PWR_TIME register. The PWRRDY bit in the STATUS0 register

is set after PWR_TIME + 1 samples accumulate at 8 kSPS. The

maximum value of the PWR_TIME register is 8191 decimals, and

the maximum power accumulation time is 1.024 sec.

The xSIGN bits in the PHSIGN register indicate the sign of

accumulated powers over the PWR_TIME interval. The PWR_

SIGN_SEL[1:0] bits allow the user to select whether the power sign

change follows the total or fundamental energies. When sign of the

accumulated power changes, the corresponding REVx bits in the

STATUS0 register are set and IRQ0 generates an interrupt.

The ADE9430 allows the user to accumulate total active power

and VAR powers into separate positive and negative values into

the PWATT_ACC and NWATT_ACC, and PVAR_ACC and NVAR_

ACC registers. A new accumulation from zero begins when the

power update interval set in PWR_TIMER elapses.

See the ADE9430 Technical Reference Manual for additional infor-

mation.

Digital to Frequency Conversion—CFx Output

The ADE9430 includes four pulse outputs that are proportional

to the energy accumulation in the CF1 through CF4 output pins.

Figure 48 shows a block diagram of the CFx pulse generation. CF3

is multiplexed with ZX, and CF4 is multiplexed with EVENT and

DREADY.

See the ADE9430 Technical Reference Manual for additional infor-

mation.

Figure 48. Digital to Frequency Conversion for CFx

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