ADE9430 datasheet(29/35 Pages) AD

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Data Sheet

ADE9430

THEORY OF OPERATION

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Rev. 0 | 29 of 35

Energy and Phase Selection

The CFxSEL bits in the CFMODE register select which type of

energy to output on the CFx pins. The TERMSELx bits in the

COMPMODE register select which phase energies to include in the

CFx output.

For example, with CF1SEL = 000 and TERMSEL1 = 111, CF1

indicates the total active power output of Phase A, Phase B, and

Phase C.

See the ADE9430 Technical Reference Manual for additional infor-

mation.

Configuring the CFx Pulse Width

The value of the CFx_LT and the CF_LTMR bits in the CF_LCFG

The maximum CFx with threshold (xTHR) = 0x00100000 and

CFxDEN = 2 is 78.9 kHz. It is recommended to have xTHR =

0x00100000.

See the ADE9430 Technical Reference Manual for additional infor-

mation.

CFx Pulse Sign

The SUMxSIGN bits in the PHSIGN register indicate whether the

sum of the energy that went into the last CFx pulse is positive or

negative. The REVPSUMx bits in the STATUS0 register and the

EVENT_STATUS register indicate if the CFx polarity changed sign.

This feature generates an interrupt on IRQ0.

See the ADE9430 Technical Reference Manual for additional infor-

mation.

Clearing the CFx Accumulator

To clear the accumulation in the digital to frequency converter and

CFDEN counter, write 1 to the CF_ACC_CLR bit in the CONFIG1

ADE9430 Technical Reference Manual for additional information.

POWER QUALITY MEASUREMENTS

Zero-Crossing Detection

The ADE9430 offers zero-crossing detection on the VA, VB, VC,

IA, IB, and IC input signals. The neutral current channel, IN, does

not contain a zero-crossing detection circuit. Figure 49 and Figure

50 show the current and voltage channel datapaths preceding

zero-crossing detection.

Use the ZX_SRC_SEL bit in the CONFIG0 register to select data

before the high-pass filter or after phase compensation to configure

the inputs to zero-crossing detection. ZX_SRC_SEL is zero by

default after reset.

To provide protection from noise, voltage channel zero-crossing

events (ZXVA, ZXVB, and ZXVC) do not generate if the absolute

value of the LPF1 output voltage is smaller than the threshold,

ZXTHRSH. The current channel zero-crossing detection outputs

(ZXIA, ZXIB, and ZXIC) are active for all input signals levels.

Calculate the zero-crossing threshold, ZXTHRSH, from the follow-

ing equation:

ZXTHRSH =

V_PCFatFullScale × LPF1Attenuation

x×32×28

(10)

where:

V_PCF at Full Scale is ±74,532,013 decimal.

LPF1 Attenuation is 0.86 at 50 Hz and 0.81 at 60 Hz.

x is the dynamic range below which the voltage channel zero-cross-

ing must be blocked.

The ADE9430 can calculate the combined zero crossings for all

three phases as (VA + VB − VC)/2 by configuring the ZX_SEL bits

in the ZX_LP_SEL register. If VCONSEL is not equal to 0, the VB

component in the combined zero-crossing circuit is set to zero.

The zero-crossing detection circuits have two different output rates:

8 kSPS and 1024 kSPS. The 8 kSPS zero-crossing signal calcu-

lates the line period, updates the ZXx bits in the STATUS1 register,

and monitors the zero-crossing timeout, phase sequence error de-

tection, resampling, and energy accumulation functions. The 1024

kSPS zero-crossing signal calculates the angle and updates the

zero-crossing output on the CF3/ZX pin.

See the ADE9430 Technical Reference Manual for additional infor-

mation.

Figure 49. Voltage Channel Signal Chain Preceding Zero-Crossing Detection

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