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DVR 数据表(PDF) 178 Page - Microchip Technology |
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DVR 数据表(HTML) 178 Page - Microchip Technology |
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178 / 416 page  PIC24FJ256GA705 FAMILY DS30010118D-page 178 2016-2018 Microchip Technology Inc. REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2(2) ENFLT1(2) bit 15 bit 8 R/W-0 HSC/R/W-0 HSC/R/W-0 HSC/R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ENFLT0(2) OCFLT2(2,3) OCFLT1(2,4) OCFLT0(2,4) TRIGMODE OCM2(1) OCM1(1) OCM0(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Output Compare x Stop in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode bit 12-10 OCTSEL<2:0>: Output Compare x Timer Select bits 111 = Peripheral clock (FCY) 110 = Reserved 101 = Reserved 100 = Timer1 clock (only synchronous clock is supported) 011 = Unimplemented 010 = Unimplemented 001 = Timer3 clock 000 = Timer2 clock bit 9 ENFLT2: Fault Input 2 Enable bit(2) 1 = Fault 2 (Comparator 1/2/3 out) is enabled(3) 0 = Fault 2 is disabled bit 8 ENFLT1: Fault Input 1 Enable bit(2) 1 = Fault 1 (OCFB pin) is enabled(4) 0 = Fault 1 is disabled bit 7 ENFLT0: Fault Input 0 Enable bit(2) 1 = Fault 0 (OCFA pin) is enabled(4) 0 = Fault 0 is disabled bit 6 OCFLT2: Output Compare x PWM Fault 2 (Comparator 1/2/3) Condition Status bit(2,3) 1 = PWM Fault 2 has occurred 0 = No PWM Fault 2 has occurred bit 5 OCFLT1: Output Compare x PWM Fault 1 (OCFB pin) Condition Status bit(2,4) 1 = PWM Fault 1 has occurred 0 = No PWM Fault 1 has occurred bit 4 OCFLT0: PWM Fault 0 (OCFA pin) Condition Status bit(2,4) 1 = PWM Fault 0 has occurred 0 = No PWM Fault 0 has occurred Note 1: The OCx output must also be configured to an available RPn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”. 2: The Fault input enable and Fault status bits are valid when OCM<2:0> = 111 or 110. 3: The Comparator 1 output controls the OC1-OC3 channels. 4: The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”. |
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