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DVR 数据表(PDF) 92 Page - Microchip Technology |
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DVR 数据表(HTML) 92 Page - Microchip Technology |
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92 / 416 page ![]() PIC24FJ256GA705 FAMILY DS30010118D-page 92 2016-2018 Microchip Technology Inc. REGISTER 8-2: CORCON: CPU CORE CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 R/W-1 U-0 U-0 — — — —IPL3(2) PSV — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’= Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 2 PSV: Not used as part of the interrupt module bit 1-0 Unimplemented: Read as ‘0’ Note 1: For complete register details, see Register 3-2. 2: The IPL<2:0> Status bits are concatenated with the IPL3 Status bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. User interrupts are disabled when IPL3 = 1. |
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