DVR datasheet(80/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 80

 2016-2018 Microchip Technology Inc.

RCON: RESET CONTROL REGISTER

R/W-0

R/W-1

R/W-0

U-0

R/W-0

TRAPR(1)

IOPUWR(1)

SBOREN(5)

RETEN(2)

—

—CM(1)

VREGS(3)

bit 15

bit 8

R/W-0

R/W-1

EXTR(1)

SWR(1)

SWDTEN(4)

WDTO(1)

SLEEP(1)

IDLE(1)

BOR(1)

POR(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

TRAPR: Trap Reset Flag bit(1)

1 = A Trap Conflict Reset has occurred

0 = A Trap Conflict Reset has not occurred

bit 14

IOPUWR: Illegal Opcode or Uninitialized W Register Access Reset Flag bit(1)

1 = An illegal opcode detection, an illegal address mode or Uninitialized W register is used as an

Address Pointer and caused a Reset

0 = An illegal opcode or Uninitialized W register Reset has not occurred

bit 13

SBOREN: Software Control Over the BOR Function bit(5)

1 = BOR is enabled

0 = BOR is disabled

bit 12

RETEN: Retention Mode Enable bit(2)

1 = Retention mode is enabled while device is in Sleep mode (1.2V regulator supplies to the core)

0 = Retention mode is disabled; normal voltage levels are present

bit 11-10

Unimplemented: Read as ‘0’

bit 9

CM: Configuration Word Mismatch Reset Flag bit(1)

1 = A Configuration Word Mismatch Reset has occurred

0 = A Configuration Word Mismatch Reset has not occurred

bit 8

VREGS: Fast Wake-up from Sleep bit(3)

1 = Fast wake-up is disabled (lower power)

0 = Fast wake-up is enabled (higher power)

bit 7

EXTR: External Reset (MCLR) Pin bit(1)

1 = A Master Clear (pin) Reset has occurred

0 = A Master Clear (pin) Reset has not occurred

bit 6

SWR: Software RESET (Instruction) Flag bit(1)

1 = A RESET instruction has been executed

0 = A RESET instruction has not been executed

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the LPCFG Configuration bit is ‘1’ (unprogrammed), the retention regulator is disabled and the RETEN

bit has no effect. Retention mode preserves the SRAM contents during Sleep.

3: Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from Sleep.

Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring.

4: If the FWDTEN<1:0> Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless

of the SWDTEN bit setting.

5: The BOREN<1:0> (FPOR<1:0>) Configuration bits must be set to ‘01’ in order for SBOREN to have an effect.

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