DVR datasheet(16/416 Pages) MICROCHIP

16 / 416 page

PIC24FJ256GA705 FAMILY

DS30010118D-page 16

 2016-2018 Microchip Technology Inc.

1.2

DMA Controller

PIC24FJ256GA705 family devices have a Direct Memory

Access (DMA) Controller. This module acts in concert

with the CPU, allowing data to move between data mem-

ory and peripherals without the intervention of the CPU,

increasing data throughput and decreasing execution

time overhead. Six independently programmable

channels make it possible to service multiple peripherals

at virtually the same time, with each channel peripheral

performing a different operation. Many types of data

transfer operations are supported.

1.3

Other Special Features

• Peripheral Pin Select: The Peripheral Pin Select

(PPS) feature allows most digital peripherals to be

mapped over a fixed set of digital I/O pins. Users

may independently map the input and/or output of

any one of the many digital peripherals to any one

of the I/O pins.

• Configurable Logic Cell: The Configurable

Logic Cell (CLC) module allows the user to

specify combinations of signals as inputs to a

logic function and to use the logic output to control

other peripherals or I/O pins.

• Timing Modules: The PIC24FJ256GA705 family

provides three independent, general purpose,

16-bit timers (two of which can be combined

into a 32-bit timer). The devices also include

four multiple output advanced

Capture/Compare/PWM/Timer peripherals, and

three independent legacy Input Capture and

three independent legacy Output Compare modules.

• Communications: The PIC24FJ256GA705 family

incorporates a range of serial

communication peripherals to handle a range of

application requirements. There are two indepen-

dent I2C modules that support both Master and

Slave modes of operation. Devices also have,

through the PPS feature, two independent UARTs

with built-in IrDA® encoders/decoders and

three SPI modules.

• Analog Features: All members of the

PIC24FJ256GA705 family include a 12-bit A/D

Converter (A/D) module and a triple comparator

module. The A/D module incorporates a range of

new features that allow the converter to assess

and make decisions on incoming data, reducing

CPU overhead for routine A/D conversions. The

comparator module includes three analog

comparators that are configurable for a wide

range of operations.

• CTMU Interface: In addition to their other analog

features, members of the PIC24FJ256GA705

family include the CTMU interface module. This

provides a convenient method for precision time

measurement and pulse generation, and can serve

as an interface for capacitive sensors.

• Enhanced Parallel Master/Parallel Slave Port:

This module allows rapid and transparent access to

the microcontroller data bus, and enables the CPU

to directly address external data memory. The

parallel port can function in Master or Slave mode,

accommodating data widths of four or eight bits and

address widths of up to ten bits in Master modes.

• Real-Time Clock and Calendar (RTCC): This

module implements a full-featured clock and

calendar with alarm functions in hardware, freeing

up timer resources and program memory space

for use of the core application.

1.4

Details on Individual Family

Members

Devices in the PIC24FJ256GA705 family are available

in 28-pin, 44-pin and 48-pin packages. The general

block diagram for all devices is shown in Figure 1-1.

The devices are differentiated from each other in

five ways:

Flash program memory (64 Kbytes for

PIC24FJ64GA70X devices, 128 Kbytes for

PIC24FJ128GA70X devices, 256 Kbytes for

PIC24FJ256GA70X devices).

Available I/O pins and ports (22 pins on two

ports for 28-pin devices, and 36 and 40 pins on

three ports for 44-pin/48-pin devices).

Enhanced Parallel Master Port (EPMP) is only

available on 44-pin/48-pin devices.

Analog input channels (10 channels for 28-pin

devices and 14 channels for 44-pin/48-pin

devices).

CTMU input channels (12 channels for 28-pin

devices and 13 channels for 44-pin/48-pin

devices)

All other features for devices in this family are identical.

These are summarized in Table 1-1 and Table 1-2.

A list of the pin features available on the

PIC24FJ256GA705 family devices, sorted by func-

tion, is shown in Table 1-3. Note that this table shows

the pin location of individual peripheral features and not

how they are multiplexed on the same pin. This

information is provided in the pinout diagrams in the

beginning of this data sheet. Multiplexed features are

sorted by the priority given to a feature, with the highest

priority peripheral being listed first.

DVR 数据表(PDF) 16 Page - Microchip Technology

DVR 数据表(HTML) 16 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载