DVR datasheet(91/416 Pages) MICROCHIP

91 / 416 page

 2016-2018 Microchip Technology Inc.

DS30010118D-page 91

PIC24FJ256GA705 FAMILY

SR: ALU STATUS REGISTER(1)

U-0

R/W-0

—

bit 15

bit 8

R/W-0(3)

R-0

R/W-0

IPL2(2)

IPL1(2)

IPL0(2)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’= Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-5

IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)

111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled

110 = CPU Interrupt Priority Level is 6 (14)

101 = CPU Interrupt Priority Level is 5 (13)

100 = CPU Interrupt Priority Level is 4 (12)

011 = CPU Interrupt Priority Level is 3 (11)

010 = CPU Interrupt Priority Level is 2 (10)

001 = CPU Interrupt Priority Level is 1 (9)

000 = CPU Interrupt Priority Level is 0 (8)

Note 1:

For complete register details, see Register 3-1.

The IPL<2:0> Status bits are concatenated with the IPL3 Status bit (CORCON<3>) to form the CPU

Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. User interrupts

are disabled when IPL3 = 1.

The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.

DVR 数据表(PDF) 91 Page - Microchip Technology

DVR 数据表(HTML) 91 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载