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DVR 数据表(PDF) 73 Page - Microchip Technology

部件名 DVR
功能描述  16-Bit General Purpose Microcontrollers with 256-Kbyte Flash and 16-Kbyte RAM in Low Pin Count Packages
PDF  416 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

DVR 数据表(HTML) 73 Page - Microchip Technology

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 2016-2018 Microchip Technology Inc.
DS30010118D-page 73
PIC24FJ256GA705 FAMILY
REGISTER 6-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
HC/R/S-0(1)
R/W-0(1)
HSC/R-0(1)
R/W-0
r-0
r-0
U-0
U-0
WR
WREN
WRERR
NVMSIDL
bit 15
bit 8
U-0
U-0
U-0
U-0
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0(1)
—NVMOP3(2)
NVMOP2(2)
NVMOP1(2)
NVMOP0(2)
bit 7
bit 0
Legend:
S = Settable bit
HC = Hardware Clearable bit
r = Reserved bit
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
HSC = Hardware Settable/Clearable bit
bit 15
WR: Write Control bit(1)
1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once the operation is complete
0 = Program or erase operation is complete and inactive
bit 14
WREN: Write Enable bit(1)
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
bit 13
WRERR: Write Sequence Error Flag bit(1)
1 = An improper program or erase sequence attempt, or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12
NVMSIDL: NVM Stop in Idle bit
1 = Removes power from the program memory when device enters Idle mode
0 = Powers program memory in Standby mode when the device enters Idle mode
bit 11-10
Reserved: Maintain as ‘0’
bit 9-4
Unimplemented: Read as ‘0’
bit 3-0
NVMOP<3:0>: NVM Operation Select bits(1,2)
1110 = Chip erases user memory (does not erase Device ID, customer OTP or executive memory)
0100 = Unused
0011 = Erases a page of program or executive memory
0010 = Row programming operation
0001 = Double-word programming operation
Note 1:
These bits can only be reset on a Power-on Reset.
2:
All other combinations of NVMOP<3:0> are unimplemented.



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