DVR datasheet(185/416 Pages) MICROCHIP

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DS30010118D-page 185

PIC24FJ256GA705 FAMILY

16.2

General Purpose Timer

Timer mode is selected when CCSEL = 0 and

MOD<3:0> = 0000. The timer can function as a 32-bit

timer or a dual 16-bit timer, depending on the setting of

the T32 bit (Table 16-1).

TABLE 16-1:

TIMER OPERATION MODE

Dual 16-Bit Timer mode provides a simple timer function

with two independent 16-bit timer/counters. The primary

timer uses the CCPxTMRL and CCPxPRL registers.

Only the primary timer can interact with other modules

on the device. It generates the MCCPx Sync out signals

for use by other MCCPx modules. It can also use the

SYNC<4:0> bits signal generated by other modules.

The secondary timer uses the CCPxTMRH and

CCPxPRH registers. It is intended to be used only as a

periodic interrupt source for scheduling CPU events. It

does not generate an output Sync/Trigger signal like the

primary time base. In Dual Timer mode, the Timer Period

High register, CCPxPRH, generates the MCCPx

compare event (CCPxIF) used by many other modules

on the device.

The 32-Bit Timer mode uses the CCPxTMRL and

CCPxTMRH registers, together, as a single 32-bit timer.

When CCPxTMRL overflows, CCPxTMRH increments

by one. This mode provides a simple timer function

when it is important to track long time periods. Note that

the T32 bit (CCPxCON1L<5>) should be set before the

CCPxTMRL or CCPxPRH registers are written to

initialize the 32-bit timer.

16.2.1

SYNC AND TRIGGER OPERATION

In both 16-bit and 32-bit modes, the timer can also

function in either Synchronization (“Sync”) or Trigger

mode operation. Both use the SYNC<4:0> bits

(CCPxCON1H<4:0>) to determine the input signal

source. The difference is how that signal affects the timer.

In Sync operation, the Timer Reset or clear occurs when

the input selected by SYNC<4:0> is asserted. The timer

immediately begins to count again from zero unless it is

held for some other reason. Sync operation is used when-

ever the TRIGEN bit (CCPxCON1H<7>) is cleared. The

SYNC<4:0> bits can have any value except ‘11111’.

In Trigger mode operation, the timer is held in Reset

until the input selected by SYNC<4:0> is asserted;

when it occurs, the timer starts counting. Trigger oper-

ation is used whenever the TRIGEN bit is set. In Trigger

mode, the timer will continue running after a trigger

event as long as the CCPTRIG bit (CCPxSTATL< 7>)

is set. To clear CCPTRIG, the TRCLR bit

(CCPxSTATL<5>) must be set to clear the trigger

event, reset the timer and hold it at zero until another

trigger event occurs. On PIC24FJ256GA705 family

devices, Trigger mode operation can only be used

when the system clock is the time base source

(CLKSEL<2:0> = 000).

FIGURE 16-3:

DUAL 16-BIT TIMER MODE

T32

(CCPxCON1L<5>)

Operating Mode

Dual Timer Mode (16-bit)

Timer Mode (32-bit)

Comparator

CCPxTMRL

CCPxPRL

CCPxRB

CCPxTMRH

CCPxPRH

Comparator

Clock

Sources

Set CCTxIF

Special Event Trigger

Set CCPxIF

SYNC<4:0>

Time Base

Generator

Sync/

Trigger

Control

Comparator

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