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DVR 数据表(PDF) 242 Page - Microchip Technology |
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DVR 数据表(HTML) 242 Page - Microchip Technology |
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242 / 416 page  PIC24FJ256GA705 FAMILY DS30010118D-page 242 2016-2018 Microchip Technology Inc. REGISTER 20-1: PMCON1: EPMP CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 PMPEN — PSIDL ADRMUX1 ADRMUX0 —MODE1 MODE0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP ALMODE — BUSKEEP IRQM1 IRQM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PMPEN: Parallel Master Port Enable bit 1 = EPMP is enabled 0 = EPMP is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 PSIDL: Parallel Master Port Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits 11 = Lower address bits are multiplexed with data bits using three address phases 10 = Lower address bits are multiplexed with data bits using two address phases 01 = Lower address bits are multiplexed with data bits using one address phase 00 = Address and data appear on separate pins bit 10 Unimplemented: Read as ‘0’ bit 9-8 MODE<1:0>: Parallel Port Mode Select bits 11 = Master mode 10 = Enhanced PSP; pins used are PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0> 01 = Buffered PSP; pins used are PMRD, PMWR, PMCS and PMD<7:0> 00 = Legacy Parallel Slave Port; pins used are PMRD, PMWR, PMCS and PMD<7:0> bit 7-6 CSF<1:0>: Chip Select Function bits 11 = Reserved 10 = PMA14 is used for Chip Select 1 01 = Reserved 00 = PMCS2 is used for Chip Select 2, PMCS1 is used for Chip Select 1 bit 5 ALP: Address Latch Polarity bit 1 = Active-high (PMALL, PMALH and PMALU) 0 = Active-low (PMALL, PMALH and PMALU) bit 4 ALMODE: Address Latch Strobe Mode bit 1 = Enables “smart” address strobes (each address phase is only present if the current access would cause a different address in the latch than the previous address) 0 = Disables “smart” address strobes bit 3 Unimplemented: Read as ‘0’ bit 2 BUSKEEP: Bus Keeper bit 1 = Data bus keeps its last value when not actively being driven 0 = Data bus is in a high-impedance state when not actively being driven bit 1-0 IRQM<1:0>: Interrupt Request Mode bits 11 = Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode), or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only) 10 = Reserved 01 = Interrupt is generated at the end of a read/write cycle 00 = No interrupt is generated |
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