DVR datasheet(270/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 270

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21.6.1

POWER CONTROL CLOCK SOURCE

The stability and sample windows are controlled by

the PWCSAMPx and PWCSTABx bit fields in the

RTCCON3L register (RTCCON3L<15:8> and <7:0>,

respectively). As both the stability and sample windows

are defined in terms of the RTCC clock, their

absolute values vary by the value of the PWC clock

base period (TPWCCLK). For example, using a

32.768 kHz SOSC input clock would produce a

TPWCCLK of 1/32768 = 30.518 µs. The 8-bit magnitude

of PWCSTABx and PWCSAMPx allows for a window

size of 0 to 255 TPWCCLK. The period of the PWC clock

can also be adjusted with a 1:1, 1:16, 1:64 or

1:256 prescaler, determined by the PWCPS<1:0> bits

(RTCCON2L<7:6>).

In addition, certain values for the PWCSTABx and

PWCSAMPx fields have specific control meanings in

determining power control operations. If either bit field is

00h, the corresponding window is inactive. In addition, if

the PWCSTABx field is FFh, the stability window

remains active continuously, even if power control is

disabled.

21.7

Event Timestamping

The RTCC includes a set of Timestamp registers that

may be used for the capture of Time and Date register

values when an external input signal is received. The

RTCC will trigger a timestamp event when a low pulse

occurs on the TMPRN pin.

21.7.1

TIMESTAMP OPERATION

The event input is enabled for timestamping using the

TSAEN bit (RTCCON1L<0>). When the timestamp event

occurs, the present time and date values will be stored in

the TSATIMEL/H and TSADATEL/H registers, the

TSAEVT status bit (RTCSTATL<3>) will be set and an

RTCC interrupt will occur. A new timestamp capture event

cannot occur until the user clears the TSAEVT status bit.

21.7.2

MANUAL TIMESTAMP OPERATION

The current time and date may be captured in the

TSATIMEL/H and TSADATEL/H registers by writing a

‘1’ to the TSAEVT bit location while the timestamp func-

tionality is enabled (TSAEN = 1). This write will not set

the TSAEVT bit, but it will initiate a timestamp capture.

The TSAEVT bit will be set when the capture operation

is complete. The user must poll the TSAEVT bit to

determine when the capture operation is complete.

After the Timestamp registers have been read, the

TSAEVT bit should be cleared to allow further

hardware or software timestamp capture events.

Note 1: The TSATIMEL/H and TSADATEL/H regis-

ter pairs can be used for data storage when

TSAEN = 0. The values of TSATIMEL/H

and TSADATEL/H will be maintained

throughout all types of non-Power-on

Resets (MCLR, WDT, etc).

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