DVR datasheet(101/416 Pages) MICROCHIP

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DS30010118D-page 101

PIC24FJ256GA705 FAMILY

bit 4

Unimplemented: Read as ‘0’

bit 3

CF: Clock Fail Detect bit

1 = FSCM has detected a clock failure

0 = No clock failure has been detected

bit 2

POSCEN: Primary Oscillator Sleep Enable bit

1 = Primary Oscillator continues to operate during Sleep mode

0 = Primary Oscillator is disabled during Sleep mode

bit 1

SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit

1 = Enables Secondary Oscillator

0 = Disables Secondary Oscillator

bit 0

OSWEN: Oscillator Switch Enable bit

1 = Initiates an oscillator switch to a clock source specified by the NOSC<2:0> bits

0 = Oscillator switch is complete

OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED)

Note 1:

OSCCON is protected by a write lock to prevent inadvertent clock switches. See Section 9.4 “Clock

Switching Operation” for more information.

Reset values for these bits are determined by the FNOSCx Configuration bits.

The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In

addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.

This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

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