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DS30010118D-page 113

PIC24FJ256GA705 FAMILY

10.0 POWER-SAVING FEATURES

The PIC24FJ256GA705 family of devices provides the

ability to manage power consumption by selectively

managing clocking to the CPU and the peripherals. In

general, a lower clock frequency and a reduction in the

number of circuits being clocked constitutes lower

consumed power. All PIC24F devices manage power

consumption in four different ways:

• Clock Frequency

• Instruction-Based Sleep and Idle modes

• Software Controlled Doze mode

• Selective Peripheral Control in Software

Combinations of these methods can be used to

selectively tailor an application’s power consumption,

while still maintaining critical application features, such

as timing-sensitive communications.

10.1

Clock Frequency and Clock

Switching

PIC24F devices allow for a wide range of clock

frequencies to be selected under application control. If

the system clock configuration is not locked, users can

choose low-power or high-precision oscillators by simply

changing the NOSC<2:0> bits. The process of changing

a system clock during operation, as well as limitations to

the process, are discussed in more detail in Section 9.0

“Oscillator Configuration”.

10.2

Instruction-Based Power-Saving

Modes

PIC24F devices have two special power-saving modes

that are entered through the execution of a special

PWRSAV instruction. Sleep mode stops clock operation

and halts all code execution; Idle mode halts the CPU

and code execution, but allows peripheral modules to

continue operation. The assembly syntax of the

PWRSAV instruction is shown in Example 10-1.

The MPLAB® XC16 C compiler offers “built-in” functions

for the power-saving modes as follows:

Idle();

// places part in Idle

Sleep();

// places part in Sleep

Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset. When

the device exits these modes, it is said to “wake-up”.

10.2.1

SLEEP MODE

Sleep mode has these features:

• The system clock source is shut down. If an

on-chip oscillator is used, it is turned off.

• The device current consumption will be reduced

to a minimum provided that no I/O pin is sourcing

current.

• The Fail-Safe Clock Monitor does not operate

during Sleep mode since the system clock source

is disabled.

• The LPRC clock will continue to run in Sleep

mode if the WDT is enabled.

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode.

• Some device features or peripherals may

continue to operate in Sleep mode. This includes

items, such as the Input Change Notification

(ICN) on the I/O ports or peripherals that use an

external clock input. Any peripheral that requires

the system clock source for its operation will be

disabled in Sleep mode.

The device will wake-up from Sleep mode on any of the

these events:

• On any interrupt source that is individually

enabled

• On any form of device Reset

• On a WDT time-out

On wake-up from Sleep, the processor will restart with

the same clock source that was active when Sleep

mode was entered.

EXAMPLE 10-1:

PWRSAV INSTRUCTION SYNTAX

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. For more information, refer

to the “dsPIC33/PIC24 Family Reference

Manual”,

“Power-Saving

Features

with Deep Sleep” (DS39727), which is

available from the Microchip website

(www.microchip.com). The information in

this

data

sheet

supersedes

the

information in the FRM.

Note:

SLEEP_MODE and IDLE_MODE are con-

stants defined in the assembler include

file for the selected device.

PWRSAV

#SLEEP_MODE

; Put the device into SLEEP mode

PWRSAV

#IDLE_MODE

; Put the device into IDLE mode

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