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DVR 数据表(PDF) 118 Page - Microchip Technology |
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DVR 数据表(HTML) 118 Page - Microchip Technology |
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118 / 416 page ![]() PIC24FJ256GA705 FAMILY DS30010118D-page 118 2016-2018 Microchip Technology Inc. REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — IC3MD IC2MD IC1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — OC3MD OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 IC3MD: Input Capture 3 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 9 IC2MD: Input Capture 2 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 8 IC1MD: Input Capture 1 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 7-3 Unimplemented: Read as ‘0’ bit 2 OC3MD: Output Compare 3 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Module is disabled 0 = Module power and clock sources are enabled |
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